We offer a streamlined method for configuring the Zynq MPSoC Vivado IP Core using Vivado Board Files. For detailed guidance, refer to applying the Zynq Ultrascale+ MPSoC Vivado IP Core Configuration in the Getting Started section. Further information on the provided board files can be found at Vivado Board File.

Although a standalone board file for the ECM1900 is not available, as it necessitates attachment to a mating board for power and other functionalities, we do supply the following board files:

• ECM1900-7CG W/ BRK1900
• ECM1900-7EG W/ BRK1900
• ECM1900-7EV W/ BRK1900

We recommend utilizing a configuration from the above board files when configuring the Zynq MPSoC Vivado IP Core for your custom mating board. Begin by disabling the BRK1900 specific features provided in the chosen board file, leaving only the ECM1900 configuration. Subsequently, incorporate the features supplied by your mating board. The ECM1900 W/ BRK1900 configuration serves as a reliable starting reference. The following list states which peripherals to disable in the ECM1900 W/ BRK1900 Board File configuration to obtain an ECM1900-only configuration:

• GPIO0
• GPIO1
• GEM0
• SATA
• USB1

For convenience, we provide a table reference that includes the PS peripherals present on the ECM1900 and their corresponding MIO connections. This information can assist in planning the addition of PS peripherals to your mating board. The MIO pins range from 0 to 77. In our provided table reference, any MIO pins not explicitly listed are routed to the MC connectors. Consult the Zynq UltraScale+ Device Technical Reference Manual (UG1085) for information on additional peripherals that can be placed on the remaining MIO pins. Note that some peripherals necessitate specific MIO pin groupings.

The Zynq MPSoC Vivado IP Core configuration GUI accounts for MIO pin pairing and grouping rules, issuing warnings for any overlapping assignments. We recommend using the Zynq MPSoC Vivado IP Core configuration GUI as a guide when planning the placement of added PS MIO peripherals.