The PCB revision is identified on the board silkscreen.

• DisplayPort is not supported in this revision. This is expected to be supported in a future revision.
• Voltage translation for control signals to the QSFP cages is non-functional. While transceiver routing is functional, the lack of usable control signals may render some QSFP modules inoperable on the BRK1900. A fix for this is expected in revision Bxx.
• The SATA hsrx lane polarity is inverted on the BRK1900. The hsrx_polarity_flip bit from the L2_TM_MISC1 (SERDES) register must be set. See Xilinx UG1087 for information about the Zynq UltraScale+ Devices Register Reference. A number of methods can be used to set this bit, the easiest of them is using devmem from the command line i.e. devmem 0xFD409898 32 0x0080.