The 2-GiByte DDR4 SDRAM provides a 32-bit wide data interface and is connected to the 1.2-V I/O on HP banks 70 and 71 of the FPGA. The maximum data rate of the SDRAM is 2666 Mb/s, although the speed grade of the Kintex UltraScale+ will limit the maximum supported data rate to what is stated in Table 27 of DS922. The -1 speed grade on the XEM8370 supports a maximum data rate of 2400 Mb/s. This gives a supported peak memory bandwidth of 76.8 Gb/s.

The following resources are available to help provide guidance for designs that involve this memory:

• How-To Apply DDR MIG Settings and Vivado Board File to generate AMD’s MIG IP Core.
• The RAMTester sample reads and writes this memory via FrontPanel pipe endpoints.
• The XEM8370 Pins Reference can generate a constraints file (click on Export) with complete pin mapping and I/O constraints for use in your design.

Kintex UltraScale+ devices support external, high-performance memory through the use of the Memory Interface Generator (MIG) provided by AMD. MIG produces a custom memory interface core that may be included in your design. These parameters have been used successfully within Opal Kelly but your design needs may require deviations.

All settings are based on the DDR4 SDRAM (MIG) v2.2 IP and Vivado 2022.1. This configuration sets up the correct MMCM M/D values to use an exact 100MHz reference input clock to achieve exactly 2400 Mb/s performance. This is a contradiction to the GUI reported 100.04Mhz for the selection of “9996” for “Reference Input Clock Speed (ps).” Please see AMD Article 66554 for more information regarding a similar situation.

Timing will constrain the DDR4 reference clock to 100.04Mhz in this case, which is a more pessimistic constraint versus 100Mhz. This results in the user losing 1.33 ps of usable slack for timing closure on the `c0_ddr4_ui_clk` MIG user interface clock. This is negligible and won’t produce metastable/non-functional designs due to this being a more pessimistic constraint. For this reason, we use the MIG’s propagated constraint of 100.04Mhz on the DDR4 ref clk within all our provided samples.

If an additional 1.33 ps of slack is required to meet timing, you may constrain the DDR4 ref clk to 100 Mhz in a top level constraints file and ignore the critical warnings that come as a result of overwriting this.

The FPGA to DDR4 pin mappings are shown below. These are also available in the Pins Reference when exporting a constraints file as well as the sample designs that utilize the memory.

Note: the TEN signal is not connected to the FPGA. It is wired to ground on the PCB.