Device Settings

The XEM8370 supports the FrontPanel Device Settings in the table below, accessible from the FrontPanel Application as well as the Device Settings API.

See the Expansion Connectors page for more information on VIO group I/O bank connections.

All power-related device settings require a power cycle to take effect.

All settings are non-volatile and are maintained over power cycles.

XEM8370_VIO_MODEINT320 – IPMI with Device Settings fallback – IPMI is used to set the VIO voltages. If an IPMI EEPROM is not found, Device Settings will determine the output voltages.

1 – IPMI only – IPMI is used to set the VIO voltages.

2 – SmartVIO with Device Settings fallback – If any SmartVIO (see below) peripherals are present on the VIO group, then the SmartVIO solution will be used to set the VIO rail voltage. If no SmartVIO peripherals are present, then the Device Settings configured voltage value will be used.

3 – SmartVIO only – SmartVIO is tested collectively so all present SmartVIO peripherals must result in a collective validation for any of the outputs to be enabled.

4 – Device Settings only – VIO voltages are set through the VIOx_VOLTAGE device settings.

XEM8370_VIO1_VOLTAGEINT32VIO1 output voltage specified in 10’s of mV. For example, “180” would set VIO1 = 1.8V.

Valid Range: 1.2V to 3.3V

DEFAULT: 0 (output is disabled)
XEM8370_VIO2_VOLTAGEINT32VIO2 output voltage specified in 10’s of mV. For example, “180” would set VIO2 = 1.8v.

Valid Range: 0.95V to 1.8V

DEFAULT: 0 (output is disabled)
XEM8370_VIO3_VOLTAGEINT32VIO3 output voltage specified in 10’s of mV. For example, “180” would set VIO3 = 1.8V.

Valid Range: 0.95V to 1.8V

DEFAULT: 0 (output is disabled)
XEM8370_FAN_MODEINT320=Binary mode
1=Temperature controlled mode

XEM8370_FAN_ENABLEINT32In binary mode, 0=disable, 1=enable

XEM8370_FAN_TEMP_THRESHOLDINT32In temperature controlled mode, the number here represents the threshold (in degrees Celsius) when the fan is enabled.

At THRESH, fan is enabled
At THRESH-10C, fan is disabled

XEM8370_SZG_TXR4_PORTSINT32Bitfield used to indicate which SYZYGY ports (of the 16 possible ports) are TXR4 ports. Each bit represents a SYZYGY port, with bit 0 corresponding to the first SYZYGY address and bit 15 corresponding to the last SYZYGY address. A ‘1’ indicates that a particular port is a TXR4 port.

For use with the BRK8370 this value should be set to 4096 (0x1000)

Fan Control Device Settings

You may optionally connect a fan to J2 (Molex 22-23-2031). This connector drives the input voltage (5-18 V) to the fan according to the Device Settings. For most applications, we recommend binary operating mode and enabling the fan at all times. You may optionally configure fan enable based on the FPGA die temperature. See the FanSink page for more information on the available fansink unit.

Note: Make sure the input voltage is an appropriate value for the connected fan.


The SmartVIO mode is intended for carriers that implement SYZYGY ports. In SYZYGY SmartVIO mode the VIO voltage is determined by first reading the SYZYGY DNA of all SYZYGY peripherals then solving for a SmartVIO solution. Each of the three XEM8370 VIO rails corresponds to a SYZYGY VIO group. The first 4 SYZYGY ports (ports 0 to 3) are assigned to VIO1, with the next 6 SYZYGY ports (ports 4 to 9) assigned to VIO2, and the next 6 SYZYGY ports (ports 10 to 15) assigned to VIO3. The SYZYGY port ID is determined by the ports geographical address resistor as specified in the SYZYGY DNA Specification. When XEM8370_VIO_MODE is set to 0x02 or 0x03, all ports are scanned for peripherals and entered into the SmartVIO solver to determine what VIO voltage will be set. The process is as follows:

  1. The SmartVIO controller (XEM8370) queries all detected peripherals for their SYZYGY DNA.
  2. For each SYZYGY VIO group, the controller attempts to determine the lowest voltage that will satisfy all attached peripherals and FPGA ranges.
  3. If a solution is not found, the group voltage remains disabled to protect any incompatible devices on the group.
  4. If a solution is found, the group is set to that voltage and enabled.
SYZYGY PortVIO Group Geographical Address (i2c address)R_GA ADDRESS RESSISTOR (kΩ)
SYZYGY 0VIO10x30 0b0110 000x210
SYZYGY 1VIO10x31 0b0110 001x84.5
SYZYGY 2VIO10x32 0b0110 010x49.9
SYZYGY 3VIO10x33 0b0110 011x34.0
SYZYGY 4VIO20x34 0b0110 100x24.9
SYZYGY 5VIO20x35 0b0110 101x18.7
SYZYGY 6VIO20x36 0b0110 110x14.3
SYZYGY 7VIO20x37 0b0110 111x11.3
SYZYGY 8VIO20x38 0b0111 000x8.87
SYZYGY 9VIO20x39 0b0111 001x6.98
SYZYGY 10VIO30x3A 0b0111 010x5.36
SYZYGY 11VIO30x3B 0b0111 011x4.02
SYZYGY 12VIO30x3C 0b0111 100x2.94
SYZYGY 13VIO30x3D 0b0111 101x2.00
SYZYGY 14VIO30x3E 0b0111 110x1.18
SYZYGY 15VIO30x3F 0b0111 111x0.487
XEM8370 SYZYGY Port VIO Group Distribution

IPMI Controlled VIO

The XEM8370 adjustable voltage rails can be configured automatically by the carrier board. This requires a compatible EEPROM to be included and programed on the carrier board. For more information see the Adjustable I/O Voltages section of the Expansion Connectors page.