Hardware Design Guide

This reference is provided to help guide you through the design process of a mating peripheral to the XEM8370. It is not intended to be a comprehensive instruction manual. While we put forth great effort to reduce the effort required to build an FPGA-enabled platform, there are hundreds of pages of product documentation from AMD that should be considered. Use this guide as a roadmap and starting point for your design effort.

Useful References

Electrical Design Guide

Input Power Supply Connection

Input power to the XEM8370 may be applied either through the DC barrel jack or through mezzanine header MC2. For information on the barrel jack dimensions and polarity, see Powering the XEM8370. For information on mezzanine header pin assignments, see the Pins List.

Total Power Budget

The total operating power budget is an important system consideration. The power budget for the XEM8370 is highly dependent on the FPGA’s operating parameters and this can only be determined in the context of an actual target design.

The onboard XEM8370 power supply regulators provide power for all on-board systems, including the user-adjustable VIO rails provided to the mezzanine headers. The Power Budget table on the Powering the XEM8370 page indicates the total current available for each supply rail. This table may be used to estimate the total amount of input power required for your design.

FPGA I/O Bank Selection and I/O Standard

Details on the available standards can be found in the following AMD documentation:

FPGA I/O Bank Selection and Voltage

Voltage supply rails VIO1, VIO2 and VIO3 power the FPGA I/O banks routed to the expansion connectors. For information on configuring these voltages using FrontPanel, see the Device Settings page in the XEM8370 documentation. See the Expansion Connectors page for details about FPGA bank power assignments. See the XEM8370 Pins Reference for details about VIO power connections to the expansion connectors.

Mechanical Design Guide

Mezzanine Connector Placement

Refer to the XEM8370 mating board diagram for placement locations of the connectors, mounting holes, and jack screw standoffs. This diagram can be found on the Specifications page.

Confirm the Connector Footprint

For recommended PCB layout of the QTH connector, refer to the QTH footprint drawing provided by Samtec.

Confirm Mounting Hole Locations

Refer to the XEM8370 specifications for a comprehensive mechanical drawing. Also refer to the BRK8370 as a reference platform. The BRK8370 design files can be found in the Downloads section of the Pins website.

Refer to the Samtec jack screw standoff instructions for information on using the jack screws to mate and unmate the XEM8370 module to the carrier board. For our version of these instructions, please visit Jack Screw Instructions.

Confirm Other Mechanical Placements

Refer to the XEM8370 mechanical drawing for locations of the USB-C jack and the DC power jack. This drawing is available on the Specifications page.

Thermal Dissipation Requirements

Thermal dissipation for the XEM8370 is highly dependent on the FPGA’s operating parameters and this can only be determined in the context of an actual target design.

An active FPGA cooling solution is recommended for any design with high power consumption. Opal Kelly provides an optional fansink designed to clip onto the XEM8370. See the FanSink page for more information. Some designs may require a different cooling solution. Thermal analysis and simulation may be required.

Determine the Mated Board Stacking Height

The Samtec QSH-series connectors on the XEM8370 mate with QTH-series connectors on the carrier board. The QTH series is available in several stacking height options from 5 to 25 mm. The stack height is determined by the “lead style” of the QTH connector. See the Expansion Connectors page for different stacking height options.

Note that increased stack height can lead to decreased high-speed channel performance. Information on 3-dB insertion loss point is available at the Samtec product page linked above.