Clock Oscillators
Note: The clock oscillators are separate and not synchronous to the clock provided by the USB host interface.
In addition to the USB host interface clock, one fixed-frequency clock oscillators provide a fabric clock for various FPGA components and systems. Two MGT reference clocks oscillator footprints are available on board, but are not populated. Additional application specific fabric and refclock inputs can be attached to the expansion connectors.
| CLOCK | FREQUENCY | FPGA PINS (P / N) | Designator | Status |
|---|---|---|---|---|
| okHost | 100.8 Mhz | Present | ||
| Fabric | 100 MHz | E22 / E23 (Bank 70) | U31 or U32 | Present |
| MGT GTY | 156.25 MHz | N29 / N30 (Bank 129 – Refclk1) | U35 or U36 | NOT PLACED |
| MGT GTH | 156.25 MHz | T6 / T5 (Bank 226 – Refclk 1) | U37 or U38 | NOT PLACED |
General Purpose Clocks
One fabric fixed clock oscillator is on board the XEM8370 (listed above). Alternate clock frequencies can be supplied to the clock input capable pins of the expansion connectors. See the Pins List for connection details.
The Kintex UltraScale+ Clock Management Tiles (CMTs) are located adjacent to each of the HP banks available on the XEM8370. Each CMT contains one MMCM and two PLLs that can be used for various clocking features. The on board general purpose fabric clock oscillator is routed to clock capable pins of HP bank 70, allowing direct access to that bank’s CMT or access to the clock tree to reach other parts of the die with minimal skew. The clock is LVDS, terminated, biased, and AC-coupled following the circuit laid out in Figure 1‐83 of UG571.
Transceiver Reference Clock
There are two refclock oscillators on board the XEM8370 (listed above), but these parts are not placed by default. Each oscillator has two footprint options available, a 2.5×2.0mm 6 pin and a 3.2×2.5mm 6 pin. Each MGT quad has its refclock 0 input brought out to the expansion connectors. See the Pins List for connection details.
Reference clocks connected to the transceiver banks only have direct connection to the QPLLs and CPLLs within the transceiver bank’s COMMON block. The QPLL and CPLL have limited ability to multiply and divide a reference clock, making a fixed frequency reference clock unable to satisfy all protocol line rates (DisplayPort, JESD, HDMI, 10G Ethernet, etc.). Specific frequencies needed for your application can be supplied to the refclock connections available on the expansion connectors.