A SYZYGY Standard peripheral with the following features and specifications…

• ON Semiconductor AR0330 1/3-inch CMOS digital image sensor
• 3.4 Mpixel up to 60 fps
• 196 Mp/s readout via 4-lane HiSPi
• RGB Bayer color filter array
• ERS (rolling shutter) and GRR (snap-shot) modes

• Aligni PLM – See the Attachments tab for schematics.
• Camera Reference Design
• SYZYGY Specification
• SYZYGY GitHub Site – Several projects that could be helpful.
• Product Page

This data is stored in the SYZYGY DNA microcontroller on the SZG-CAMERA peripheral.

The source of the following pinout information is the SZG-CAMERA schematic. This pinout follows the SYZYGY specification for STD ports.

• Column PIN NUM (J1) lists the pin number on the SYZYGY specification’s Standard Samtec connector, this is reference designator J1 in the schematic.
• Column SIGNAL NAME lists the SYZYGY specification’s name for this pin’s connection.
• Column SCHEMATIC NET lists the net name found in the SZG-CAMERA’s schematic for the connection.

The SZG-CAMERA module includes a high performance AR0330 image sensor, along with the lens and mount necessary to begin taking images. On-board regulators provide power rails necessary to run the camera and level translation is provided to maximize the available VIO range.

The SZG-CAMERA’s DNA is configured to allow a SmartVIO range of 1.8v to 3.3v.  Level translation is present on-board to convert the VIO voltage at the SYZYGY port to the 1.8v used by the image sensor.

Two linear regulators are present on the SZG-CAMERA, one at 1.8v and one at 2.8v.  The 2.8v is required for the pixel array.

Pixel information from the image sensor is communicated back to the carrier through a HiSPi interface. Configuration of the image sensor is accomplished through a series of registers programmed through an I²C connection. A series of single ended LVCMOS signals are also used to communicate with the sensor. Level translation is included for the I²C and LVCMOS signals, allowing the SZG-CAMERA peripheral to operate across a wide range of VIO voltages.

The HiSPi interface consists of 4 differential pair data lines and a clock. The HiSPi data and clock lines use an SLVS/HiVCM voltage standard that is LVDS compatible. All HiSPi signals are output from the image sensor to the FPGA, internal termination must be used on the FPGA to ensure signal integrity.

The following I²C register settings (set in order) will setup the image sensor with a set of default settings that will work for most environments. More information on each register itself can be found in the image sensor documentation.

A high-quality glass lens, plastic lens holder, and mounting hardware are included with the EVB1005.  The part and supplier information is listed below.  Sunex also has a higher-quality lens available with better optics, the DSL944.

The SZG-CAMERA is designed to be compatible with the M3-F series of autofocus lens mounts from New Scale Tech. Level translation is provided for the SPI and 2-wire interfaces on the autofocus lens mount to translate from the VIO voltage of the carrier to 3.3V I/O required by the autofocus lens mount.

Note that none of the components related to the Autofocus module are placed by default on boards sold by Opal Kelly Inc.

• AR0330 Datasheet
• SZG-CAMERA HDL for Brain-1