DDR4 Memory

The 2-GiByte DDR4 SDRAM provides a 32-bit wide data interface and is connected to the 1.2-V I/O on HP banks 66 and 67 of the FPGA. The maximum data rate of the SDRAM is 2666 Mb/s, although the speed grade of the Artix UltraScale+ will limit the maximum supported data rate to what is stated in Table 27 of DS931. The -2 speed grade on the XEM8310-AU25P supports a maximum data rate of 2400 Mb/s. This gives a supported peak memory bandwidth of 76.8 Gb/s.

The following resources are available to help provide guidance for designs that involve this memory:

  • The RAMTester sample reads and writes this memory via FrontPanel pipe endpoints.
  • The XEM8310 Pins Reference can generate a constraints file (click on Export) with complete pin mapping and I/O constraints for use in your design.

MIG Settings

Artix UltraScale+ devices support external, high-performance memory through the use of the Memory Interface Generator (MIG) provided by Xilinx. MIG produces a custom memory interface core that may be included in your design. These parameters have been used successfully within Opal Kelly but your design needs may require deviations.

All settings are based on the DDR4 SDRAM (MIG) v2.2 IP and Vivado 2022.1. This configuration sets up the correct MMCM M/D values to use an exact 100MHz reference input clock to achieve exactly 2400 Mb/s performance. This is a contradiction to the GUI reported 100.04Mhz for the selection of “9996” for “Reference Input Clock Speed (ps).” Please see Xilinx Article 66554 for more information regarding a similar situation.

Timing will constrain the DDR4 reference clock to 100.04Mhz in this case, which is a more pessimistic constraint versus 100Mhz. This results in the user losing 1.33 ps of usable slack for timing closure on the `c0_ddr4_ui_clk` MIG user interface clock. This is negligible and won’t produce metastable/non-functional designs due to this being a more pessimistic constraint. For this reason, we use the MIG’s propagated constraint of 100.04Mhz on the DDR4 ref clk within all our provided samples.

If an additional 1.33 ps of slack is required to meet timing, you may constrain the DDR4 ref clk to 100 Mhz in a top level constraints file and ignore the critical warnings that come as a result of overwriting this.

PARAMETERXEM8310-AU25P
Controller TypeDDR4 SDRAM
Controller/PHY ModeController and physical layer
Memory Device Interface Speed (ps)833
PHY to controller clock frequency ratio4:1
Reference Input Clock Speed (ps)9996
ConfigurationComponents
Memory PartMT40A512M16LY-075
SlotSingle
IO Memory Voltage1.2V
Data Width16
ECC Disabled
Data Mask and DBIDM NO DBI
Memory Address MapROW COLUMN BANK
OrderingNormal
Cas Latency17
Cas Write Latency12
Force Read and Write commands to use AutoPrechargeDisabled
Clamshell TopologyDisabled
Enable AutoPrecharge InputDisabled
Enable User Refresh and ZQCS InputDisabled
Advanced optionsDefault

DDR4 / FPGA Pin Connections

The FPGA to DDR4 pin mappings are shown below. These are also available in the Pins Reference when exporting a constraints file as well as the sample designs that utilize the memory.

DDR4 PINFPGA PIN
RESET_NL24
CKEK21
CK_tM19
CK_cL19
CS_NK26
SDRAM_1_DQSL_tD23
SDRAM_1_DQSL_cC24
SDRAM_1_DQSU_tF24
SDRAM_1_DQSU_cF25
SDRAM_2_DQSL_tF20
SDRAM_2_DQSL_cE20
SDRAM_2_DQSU_tE16
SDRAM_2_DQSU_cE17
DM0E25
DM1G24
DM2H18
DM3G15
ACT_NG25
ODTE26
DDR4 PINFPGA PIN
A0J20
A1M26
A2J19
A3L23
A4M25
A5L20
A6J21
A7M20
A8K20
A9M24
A10 / APL25
A11K25
A12 / BCL22
A13M21
A14 / WEF22
A15 / CASK23
A16 / RASK22
BA0K18
BA1L18
BG0G22
DDR4 PINFPGA PIN
D0E23
D1D25
D2D24
D3C26
D4F23
D5B25
D6D26
D7B26
D8H26
D9H22
D10G26
D11H24
D12J26
D13H21
D14J25
D15H23
D16G21
D17D19
D18F19
D19D20
D20F18
D21E18
D22G20
D23D18
D24G16
D25E15
D26H16
D27D16
D28H17
D29D15
D30G17
D31C16