Expansion Connectors

Opal Kelly Pins is an interactive online reference for the expansion connectors on all Opal Kelly FPGA integration modules. It provides additional information on pin capabilities, pin characteristics, and PCB routing.

Pins can also generate constraint files (XDC) and help you map your HDL net names to FPGA pin locations automatically.

The Pins reference for the XEM8310 may be found at the link to the right. 
XEM8310 Pins Reference

Pins Documentation

Connector Details

Three high-density, 80-pin expansion connectors are available on the bottom-side of the XEM8310 PCB. These expansion connectors provide user access to several power rails on the XEM8310, the JTAG and SYSMON interfaces on the FPGA, 149 I/O pins, and access to the GTY transceiver banks.

MC1 and MC2 are high-density expansion connectors on the XEM8310 with Samtec part number: BSE-040-01-F-D-A. MC3 is a high-speed expansion connector with Samtec part number: QSH-040-01-F-D-DP-A.

The table below lists the appropriate Samtec mating connectors for the BSE-040-01-F-D-A along with the total mated height:

BTE-040-01-F-D-A5.00mm (0.197”)
BTE-040-02-F-D-A8.00mm (0.315”)
BTE-040-03-F-D-A11.00mm (0.433”)
BTE-040-04-F-D-A 14.00mm (0.551″)
BTE-040-08-F-D-A25.00mm (0.984”)

The table below lists the appropriate Samtec mating connectors for the QSH-040-01-F-D-DP-A along with the total mated height:

QTH-040-01-F-D-DP-A5.00mm (0.197”)
QTH-040-02-F-D-DP-A8.00mm (0.315”)
QTH-040-03-F-D-DP-A11.00mm (0.433”)
QTH-040-09-F-D-DP-A 14.00mm (0.551″)
QTH-040-07-F-D-DP-A25.00mm (0.984”)


MC1 is an 80-pin high-density connector providing access to FPGA Banks 64 (HP) and 84 (HD). Bank 64 is powered by VIO1. Bank 84 is powered by VIO2.

Pin mappings for MC1 are listed on the pins page. See the Considerations for Differential Signals section below for information on expansion signal routing.


MC2 is an 80-pin high-density connector providing access to FPGA Banks 84 (HD), 86 (HD) , and 87 (HD). Bank 84 is powered by VIO2. Bank 86 and 87 are powered by VIO3.

Pin mappings for MC2 are listed on the pins page. See the Considerations for Differential Signals section below for information on expansion signal routing.


MC3 is an 80-pin high-speed connector providing access to GTY transceiver banks 224, 225, and 226. This includes connections to MGTREFCLK0 (224), MGTREFCLK1 (225), and MGTREFCLK0 (226). MC3 also provides access to FPGA Bank 67 (HP). Bank 67 is powered by 1.2V, which cannot be changed.

The provided REFCLK pins have on board AC coupling capacitors while the transceiver lanes are directly connected to MC3.

Pin mappings for MC3 are listed on the pins page. See the Considerations for Differential Signals section below for information on expansion signal routing.

FPGA Bank Connections

64HP0.95 – 1.90 VMC1VIO1VREF152 (including 4 GC pairs)
84HD1.14 – 3.40 VMC1 / MC2VIO224 (including 4 GC pairs)
86HD1.14 – 3.40 V MC2VIO324 (including 4 GC pairs)
87HD1.14 – 3.40 V MC2VIO324 (including 4 GC pairs)
67HP0.95 – 1.90 V MC31.2V25 (including 2 GC pairs)

(*) – Note: Voltage ranges specified here are the range supported by the FPGA bank itself, not the range of the power supply connected to the bank. For power supply ranges refer to Device Settings.

The supplied Bank 67 1.2V VCCO rail has a limited user capacity of 250mA. Care must be taken using this rail as any noise coupled into it could have effects on the behavioral performance of the DDR.

Setting the Expansion Connector I/O Voltages

The Artix UltraScale+ FPGA allows users to set I/O bank voltages in order to support several different I/O signal standards. High-efficiency switching regulators on the XEM8310 provides three adjustable bank voltages VIO1, VIO2 and VIO3. These are connected to the FPGA bank VCCO according to the table above. Please see the Device Settings page for information on configuring these voltages.

Clock Input Pins

Available clock pins are shown in the XEM8310 Pins Reference. You can use the filter options to display these pins.


The JTAG connections on the FPGA are wired directly to the expansion connector MC2 with 4.7kΩ pull-up resistors on TDI, TCK and TMS. The JTAG signal voltage is 1.8V. An appropriate connector (such as a 2mm connector compatible with the JTAG cable) is need on the XEM8310 carrier. Our BRK8310 has this connector and may be used as a reference.



FPGA system monitor signals are are wired directly to the expansion connector MC2.

VREFP may optionally provide a precision reference for optimal performance of the ADC. See UG580 UltraScale Architecture System Monitor for additional details.

By default, C168 is populated with a 0.1-μF decoupling capacitor so that an external voltage reference may be used. To enable the internal reference instead, the carrier must short VREFP (MC2 pin 79) to GNDADC (MC2 pin 77). Alternatively, C168 could be replace with a 0-Ω resistor.

75N14VCCADC (1.8V supplied by the XEM8310 via FB1)
77N13GNDADC (Connected to DGND via FB2)

VREFN (FPGA P13) is connected directly to GNDADC.


The Artix UltraScale+ XADC feature is routed through two 100Ω resistors to the MC2 connector. There is a 2.2 n capacitor installed across the two FPGA pins for decoupling.



By default the VBATT functionality is disabled by the 0-Ω resistor R2 connecting it to ground. If it is required in your design, R2 must be removed. Then VBATT can be accessed on MC1.

Reference Voltage Pins (Vref)

The Artix UltraScale+ supports both internal and externally-applied input voltage thresholds for some input signal standards. The XEM8310 supports these Vref applications on bank 64 (HP). See AMD documentation UG912 and UG571 for more information on using Vref.

For Bank 64, the Vref pin is routed to expansion connector MC1. If an external Vref is required for your application, a 0.022 µF – 0.47 µF capacitor can be placed in position C1 to decouple the Vref pin.

VRP Pins

The XEM8310 routes the multi-purpose VRP pin on bank 64 (HP) to the MC1 expansion connector on pin 32. To support certain IOSTANDARD‘s like MIPI on bank 64 you can remove the 0Ω R158 resistor, and insert a 240Ω resistor at R159 to connect to ground.

Bank 67’s (HP) VRP pin is connected to ground through a 240Ω resistor. Full access to bank 67’s T2U and T3L byte groups are accessible through MC3’s high-speed expansion connector.

Please see the UltraScale Architecture SelectIO Resources for more details about the VRP pin and IOSTANDARD support.

Considerations for Differential Signals

The XEM8310 PCB layout and routing has been designed with several applications in mind, including applications requiring the use of differential (LVDS) pairs. Please refer to the Artix UltraScale+ datasheet for details on using differential I/O standards with the Artix UltraScale+ FPGA.

FPGA Differential I/O Bank Voltages

In order to use differential I/O standards with the Artix UltraScale+, you must set the VCCO voltages for the appropriate banks according to the Artix UltraScale+ datasheet.

HD banks only support LVDS inputs, and only with external termination. As such termination would interfere with the I/O being used as single ended connections, this termination is not available on the XEM8310.

HP banks support LVDS inputs and outputs. The bank VCCO must be set to 1.8V to use LVDS outputs. This also allows the use of the available internal termination on LVDS inputs.

HP Bank 67 provides 12 LVDS pairs to the MC3 connector. Bank 67 is fixed at 1.2V because a portion of the bank is utilized for DDR. If an HP Bank is not powered by 1.8V then LVDS outputs are not supported. Additionally, internal termination is not available for LVDS inputs.

Please see LVDS Interface Checklist for more information. Also see DS931 for information regarding the LVDS DC Specifications on the Artix UltraScale+.

Characteristic Impedance

Single-ended fabric I/O are routed to the expansion connectors with 50Ω characteristic impedance. Differential fabric I/O and transceiver signals are routed to the expansion connectors as pairs with 100Ω differential impedance.

Differential Pair Lengths

It is desirable that the route lengths of a differential pair be matched within some specification. Care has been taken to route differential pairs on the FPGA to adjacent pins on the expansion connectors, and the length of all pairs is matched to within 5 mils (including pin/package delays). Individual PCB routing lengths for all expansion connections are available on the XEM8310 Pins Reference page. The lengths published there represent routed PCB lengths only and do not include the pin/package delays. Pin/package delay information may be obtained from the AMD design tools.

I/O State at Power On

Artix UltraScale+ FPGAs support a weak pull-up state on all I/O pins from power on until first configuration. This behavior is controlled by the PUDC_B pin. By default the XEM8310 holds the PUDC_B pin high with a 1kΩ resistor at R125, disabling the weak pull-up on all I/O pins at power on. This behavior can be changed by inserting a 1kΩ resistor at R128 and removing the 1kΩ resistor at R125, pulling the PUDC_B pin to ground.