Powering the XEM8310

The XEM8310 requires a clean, filtered, DC supply within the range of 7.5 V to 15 V.  This supply may be delivered through the barrel jack power connector (rated to 5 A max current) or through the mezzanine connector (rated to 8 A max current).

The XEM8310 power distribution system is quite complex, with several supplies designed to provide suitable, efficient power for several systems and modules. A schematic diagram of the system follows, with input (+VDCIN) shown to the left and accessible supply rails shown to the right.

Supply Heat Dissipation (IMPORTANT!!)

Due to the limited area available on the small form-factor of the XEM8310 and the density of logic provided, heat dissipation may be a concern.  This depends entirely on the end application and cannot be predicted in advance by Opal Kelly.  Heat sinks may be required on any of the devices on the XEM8310.  Of primary focus should be the FPGA (U1) and SDRAM (U4, U5).  Although the switching supplies are high-efficiency, they are very compact and consume a small amount of PCB area for the current they can provide.

If you plan to put the XEM8310 in an enclosure, be sure to consider heat dissipation in your design.

Power Supply

The XEM8310 is designed to be operated from a single power supply of 7.5 V to 15 V supplied through the DC power jack on the device.  This provides power for the several high-efficiency switching regulators on-board to provide multiple DC voltages for various components on the device as well as three adjustable supplies for the peripheral.

A block diagram of the power distribution system is shown below.

The optional fansink for the XEM8310 has an operating range of 10.8 V to 13.2 V, with a nominal operating voltage of 12 V. It is recommended to keep the external supply voltage within this range whenever the fansink is enabled.

Barrel Jack Power Connector

The barrel jack power connector on the XEM8310 is part number PJ-102AH from CUI, Inc.  It is a standard “canon-style” 2.1mm / 5.5mm jack.  The outer ring is connected to DGND.  The center pin is connected to +VDCIN.

The PJ-102AH jack is rated for 5 A maximum continuous current. Applications requiring higher current must use the mezzanine connectors for providing power to the system (rated for a maximum of 8 A).

LED Indicators

The XEM8310 includes two LED indicators for power status.

LEDOn Condition
PWR IN (D5) +VDCIN present (>2V)
PWR GOOD (D6)All on-board power supplies active and within expected range
(Does not include VIOx supplies)

Power Budget

The table below can help you determine your power budget for each supply rail on the XEM8310.  All values are highly dependent on the application, speed, usage, and so on.  Entries we have made are based on typical values presented in component datasheets or approximations based on Xilinx power estimator results.  Shaded boxes represent unconnected rails to a particular component.  Empty boxes represent data that the user must provide based on power estimates.

The user may also need to adjust parameters we have already estimated (such as FPGA VCCO values) where appropriate. All values are shown in milliwatts (mW) unless otherwise specified.

COMPONENT(S)0.85 V1.2 V1.8 V1.8 V GT3.3 V
FPGA VCCINT, VCCINT_IO, VCCBRAM
FPGA VCCAUX, VCCAUX_IO, VCCADC956
Clock oscillators165
FPGA MGTYAVCC2228
FPGA MGTYAVTT4444
FPGA MGTYVCCAUX241
FX3 USB host interface648
DDR4 VDD/VDDQ792
DDR4 VTT termination461
DDR4 VPP142
FPGA VCCO 188297
Total (mW) 1441 19016673 548
Available (mW)13,6002,4003,60081006,600
COMPONENT(S)VIO1VIO2VIO3
FPGA VCCO
SYZYGY Group 1
SYZYGY Group 2
SYZYGY Group 3
Total (mW)
Available (mW)700 mA
1.0-1.8 V
700 mA
1.2-3.3 V
700 mA
1.2-3.3 V

Note: VIO1 + VIO2 + VIO3 total power must not exceed 22,500 mW. These regulators share the output of an intermediate 5V step-down regulator.

Example FPGA Power Consumption

Xilinx Power Estimator (XPE) version 2020.2.2_1 was used to compute the following power estimates for the VCCINT supply. These are simply estimates; your design requirements may vary considerably. The numbers below indicate approximately 80% utilization.

COMPONENTPARAMETERSVCCINT POWER (mW)
Clock200 MHz GCLK, 200,000 fanout986
Clock300 MHz GCLK, 75,000 fanout628
Clock100 MHz GCLK, 100,000 fanout272
Clock667 MHz GCLK, 50,000 fanout963
Logic200 MHz, 58,000 logic LUTs, 20,000 shift registers, 20,000 distributed RAMs, 150,000 registers1,566
Logic300 MHz, 8,000 logic LUTs, 75,000 registers583
Logic667 MHz (DDR4), 16,000 logic LUTs, 50,000 registers1,149
BRAM18-bit, 200 MHz, 280 block RAMs, 50% toggle rate519
BRAM36-bit, 300 MHz, 140 block RAMs, 50% toggle rate920
DSP300 MHz, 1090 slices, 12.5% toggle rate1,503
GTY11 channels, 16.3 Gb/s727
Misc.DCM, PLL, VCCINT_IO, etc.100
Total9,916 mW
Available13,600 mW

Heat Sink

An active (fan-based) heatsink is available to install on the FPGA for cooling. The fan enable can be controlled over the FrontPanel API. See the Device Settings documentation for more information.

The fansink is Radian part number FI27/1.3+Y+T725. It has a nominal operating voltage of 12 V and a recommended operating range of 10.8 V to 13.2 V. The fansink is powered directly by the external power supply connected to the XEM8310. It is recommended to keep the external supply voltage within this range whenever the fansink is enabled.