Hardware Design Guide

This reference is provided to help guide you through the design process of a mating peripheral to the XEM8310. It is not intended to be a comprehensive instruction manual. While we put forth great effort to reduce the effort required to build an FPGA-enabled platform, there are hundreds of pages of product documentation from Xilinx that should be considered. Use this guide as a roadmap and starting point for your design effort.

Useful References

Electrical Design Guide

Input Power Supply Connection

Input power to the XEM8310 may be applied either through the DC barrel jack or through mezzanine header MC2. For information on the barrel jack dimensions and polarity, see Powering the XEM8310. For information on mezzanine header pin assignments, see the XEM8310 Pins Reference.

Total Power Budget

The total operating power budget is an important system consideration. The power budget for the XEM8310 is highly dependent on the FPGA’s operating parameters and this can only be determined in the context of an actual target design.

The onboard XEM8310 power supply regulators provide power for all on-board systems, including the user-adjustable VIO rails provided to the mezzanine headers. The Power Budget table on the Powering the XEM8310 page indicates the total current available for each supply rail. This table may be used to estimate the total amount of input power required for your design.

FPGA I/O Bank Selection and I/O Standard

Details on the available standards can be found in the following Xilinx documentation:

FPGA Transceiver Connections

The transceiver REFCLK pins available on MC3 have on board AC coupling capacitors. The transceiver data lanes are directly connected to MC3. More information about pin features is available on the pins page.

FPGA I/O Bank Selection and Voltage

Voltage supply rails VIO1, VIO2 and VIO3 power the FPGA I/O banks on mezzanine connectors MC1 and MC2. For information on configuring these voltages using FrontPanel, see the Device Settings page.

Additional capacitance on the VIO rails should be limited for maximum regulator performance and current output. We recommend a maximum of 10uF be added to each VIO rail on your design.

The FPGA I/O bank 67 on MC3 is always powered from +1.2V_DDR.

The supplied Bank 67 1.2V VCCO rail has a limited user capacity of 250mA. Care must be taken using this rail as any noise coupled into it could have effects on the behavioral performance of the DDR.

See the Expansion Connectors page for details about FPGA bank power assignments.

External VIO

If a bank VIO outside of the software selectable options is required it can be supplied to the MC pins by your design after removing jumper resistors to the onboard VIO regulators.

Extreme care must be taken when providing external VIO voltages to prevent damage. Voltage limits for multiple devices must not be exceeded. see the Device Settings page for valid voltages.

VIO RailJumper Resistor
VIO1R86
VIO2R87
VIO3R88

Selecting the ADC Reference Voltage

There are two options for the ADC reference voltage, and one of them must be implemented in your design for proper operation of the ADC. The Artix UltraScale+ provides an internal ADC reference voltage, or an external precision reference can be provided for optimal performance of the ADC. See Xilinx UG580 UltraScale Architecture System Monitor for additional details.

To enable the internal ADC reference voltage the VREFP pin available on MC2 should be shorted to ground.

To provide a precision ADC reference voltage connect an external reference voltage to the VREFP pin available on MC2.

VBATT

By default the VBATT functionality is disabled by the 0-Ω resistor R2 connecting it to ground. If it is required in your design, R2 must be removed. Then VBATT can be accessed on MC1.

VREF

If your design uses an input signal standard that requires an externally provided voltage reference, the VREF pin for Bank 64 (HP) is available on MC1. Please see the Xilinx Artix UltraScale+ documentation for more details on using external voltage references.

JTAG

A JTAG connection is available on MC2 that may be used in your design. For more information see the Expansion Connectors page.

Mechanical Design Guide

Mezzanine Connector Placement

Refer to the XEM8310 mating board diagram for placement locations of the QTH connectors, mounting holes, and jack screw standoffs. This diagram can be found on the Specifications page of the XEM8310 documentation.

Refer to the XEM8310 Specifications for a comprehensive mechanical drawing. Also refer to the BRK8310 as a reference platform. The BRK8310 design files can be found in the Downloads section of the Pins website.

Confirm the Connector Footprint

For recommended PCB footprint of the QTH and BTE connectors, refer to the footprint drawings provided by Samtec. Find the connector part numbers on the Expansion Connectors page.

Confirm Mounting Hole Locations

Refer to the XEM8310 Specifications for a comprehensive mechanical drawing. Also refer to the BRK8310 as a reference platform. The BRK8310 design files can be found in the Downloads section of the Pins website.

Confirm Other Mechanical Placements

Refer to the XEM8310 mechanical drawing for locations of the USB jacks and the DC power jack. This drawing is available on the Specifications page of the XEM8310 documentation.

Thermal Dissipation Requirements

Thermal dissipation for the XEM8310 is highly dependent on the FPGA’s operating parameters and this can only be determined in the context of an actual target design.

An active FPGA cooling solution is recommended for any design with high power consumption. Opal Kelly provides an optional fansink designed to clip onto the XEM8310. See the Powering the XEM8310 page for more information. Some designs may require a different cooling solution. Thermal analysis and simulation may be required.

Determine the Mated Board Stacking Height

The Samtec QSH and BSE-series connectors on the XEM8310 mate with QTH and BTE-series connectors on the carrier board. The QTH and BTE-series are available in several stacking height options from 5 to 25 mm. The stack height is determined by the “lead style” of the QTH connector. See the Expansion Connectors page for mating connector part numbers.

Note that increased stack height can lead to decreased high-speed channel performance. Information on 3-dB insertion loss point is available at the Samtec product page link above.