Expansion Connectors

Opal Kelly Pins is an interactive online reference for the expansion connectors on all Opal Kelly FPGA integration modules. It provides additional information on pin capabilities, pin characteristics, and PCB routing.

Pins can also generate constraint files (XDC) and help you map your HDL net names to FPGA pin locations automatically.

The Pins reference for the XEM7360 may be found at the link to the right. 


Fan Power Supply

A small 2-pin connector (Molex 53398-0271) at JP1 provides power to an optional fan for FPGA cooling. This fan is controlled by a digital fan controller as part of the Device Sensors and Device Settings capabilities. Please see the Device Settings section for details on controlling the fan.


Connector Details

Two high-density, 180-pin expansion connectors are available on the bottom-side of the XEM7360 PCB. These expansion connectors provide user access to several power rails on the XEM7360, the JTAG interface on the FPGA, and 193 dedicated I/O pins on the FPGA, including several MRCC/SRCC clock inputs. High-speed gigabit transceiver signals are also available through these expansion connectors.

The connectors on the XEM7360 are Samtec part number: QSH-090-01-L-D-A. The table below lists the appropriate Samtec mating connectors along with the total mated height. The QTH-090-01-F-D-A part is used on the BRK7360 breakout board.

QTH-090-01-F-D-A5.00mm (0.197″)
QTH-090-02-F-D-A8.00mm (0.315″)
QTH-090-03-F-D-A11.00mm (0.433″)
QTH-090-04-F-D-A16.00mm (0.630″)
QTH-090-05-F-D-A19.00mm (0.748″)
QTH-090-07-F-D-A25.00mm (0.984″)

FPGA Bank Connections

A pair of high density SAMTEC connectors provides direct access to I/O pins and Gigabit transceivers on the FPGA. The tables below illustrates the number of pins that are available on the mezzanine connectors and the number that are routed to available sites on the FPGA.

Bank 12HRVadj21.2-3.3vMC250 (includes MRCC pair)
Bank 15HRVadj11.2-3.3vMC148 (includes MRCC pair)
Bank 16HRVadj11.2-3.3vMC148 (includes MRCC pair)
Bank 32HPVadj31.2-1.8vMC247 (includes MRCC pair)
GBT – # of transceivers8

Clock Input Pins

Available clock pins are illustrated in the table below. All pins listed are multi-region clock pins.

Bank 12
Bank 15
Bank 16
Bank 32

Setting the Expansion Vadj I/O Voltages

Three programmable high-efficiency switching regulators are on the XEM7360 which control the three adjustable voltages Vadj1, Vadj2, and Vadj3. These are connected to the FPGA bank VCCIO according to the tables above. There are two ways to set these voltages:

  • Device Settings – The FrontPanel firmware supports separate non-volatile device settings that are used to set these voltages during the power-on sequence. You can manually program these using the FrontPanel API or the FrontPanel application. See the Device Settings page for information on configuring these voltages.
  • Peripheral Personality EEPROM – You can program a small EEPROM on your peripheral (the device that attaches to the XEM7360 mezzanine connectors) that can tell the FrontPanel firmware how to configure these voltages during the power-on sequence. See below for additional information.

Note: Changes to Vadj settings require a power cycle to take effect.

Peripheral Personality EEPROM

During power-on sequencing the device firmware will query an I2C EEPROM at address 0xA2 1010 001x. This EEPROM would be connected to IPMI_SDA (MC2 pin 170) and IPMI_SCL (MC2 pin 172) and uses 3.3V logic levels. If present, the firmware will attempt to read an IPMI-formatted block of data that tells it how to configure the three adjustable voltage regulators.

Opal Kelly has provided an online tool to generate the contents of this EEPROM. Simply enter the details of your product into the online form to generate a binary file that can be stored on your EEPROM. The FrontPanel application can be used to program the generated binary file into the EEPROM.


The Xilinx Kintex-7 XADC feature is routed through two 1kΩ resistors to the MC2 connector. There is a 0.01 µF capacitor installed across the two FPGA pins for decoupling.


Considerations for Differential Signals

The XEM7360 PCB layout and routing has been designed with several applications in mind, including applications requiring the use of differential (LVDS) pairs. Please refer to the Xilinx Kintex-7 datasheet for details on using differential I/O standards with the Kintex-7 FPGA.

FPGA I/O Bank Voltages

In order to use differential I/O standards with the Kintex-7, you must set the VCCO voltages for the banks in use to the appropriate voltage according to the Xilinx Kintex-7 datasheet. Please see the section above entitled “Setting the Expansion Vadj I/O Voltages” for details.

Characteristic Impedance

The characteristic impedance of all routes from the FPGA to the expansion connector is approximately 50Ω. Differential fabric I/O and transceiver signals are routed to the expansion connectors as pairs with 100Ω differential impedance.

Differential Pair Lengths

In many cases, it is desirable that the route lengths of a differential pair be matched within some specification. Care has been taken to route differential pairs on the FPGA to adjacent pins on the expansion connectors whenever possible. We have also included the lengths of the board routes for these connections to help you equalize lengths in your final application. Due to space constraints, some pairs are better matched than others.

Reference Voltage Pins (Vref)

The Xilinx Kintex-7 supports both internal and externally-applied input voltage thresholds for some input signal standards. The XEM7360 supports these Vref applications for banks 12, 15, 16, and 32. Please see the Xilinx Kintex 7 documentation for more details. In summary,

12 Vadj2 W21 MC2:10 The two VREF pins are brought out separately on
MC2 so they can be used as I/O or VREF. 
AE21 MC2:51
15 Vadj1 D16, J20 MC1:114 All four VREF pins of these two banks are connected
together to a common pin on MC1. 
16 H11, C13
32 Vadj3 AE16 MC2:114 The two VREF pins are brought out separately on
MC2. However, AE16 has a 4.7µF capacitor for
Y18 MC2:70

I/O State at Power On

Xilinx Kintex-7 FPGAs support a weak pull-up state on SelectIO pins after power-up and during configuration. This behavior is controlled by the PUDC_B pin.

The default PUDC_B configuration on the XEM7360 depends on the PCB revision.

  • On PCB revisions EXX and later, the PUDC_B pin is pulled high by default to disable internal pull-up resistors at startup.
  • On PCB revisions DXX and earlier, the PUDC_B pin is pulled low by default to enable internal pull-up resistors at startup.

To change the default behavior of your module, see the PUDC_B Configuration support page.