DDR3 Memory

The Micron DDR3 SDRAM is connected exclusively to the 1.5-v I/O on Banks 33 and 34 of the FPGA. The tables below list these connections.

The following resources are available to help provide guidance for designs that involve this memory:

  • The RAMTester sample reads and writes this memory via FrontPanel pipe endpoints.
  • The XEM7360 Pins Reference can generate a constraints file (click on Export) with complete pin mapping and I/O constraints for use in your design.

Important VREF Note

The XEM7360 applies an external voltage reference to pins AD3 and W4 for applications using DDR3 memory. When the memory is not used in a design, these pins must set to high impedance. Not doing this can lead to contention between these multi-function IO pins and the VREF supply.

Connection Tables

DDR3 PINFPGA PIN
RESETAA2
CKpW10
CKnW9
CKEAC12
CSAB12
RASAB9
CASAC9
WEAD9
DQS0pW6
DQS0nW5
DQS1pAB1
DQS1nAC1
DQS2pAA5
DQS2nAB5
DQS3pAF5
DQS3nAF4
DM0U6
DM1Y3
DM2AB6
DM3AD4
ODTAA13
DDR3 PINFPGA PIN
A0AD8
A1AC8
A2AA7
A3AA8
A4AF7
A5AE7
A6W8
A7V9
A8Y10
A9Y11
A10Y7
A11Y8
A12V7
A13V8
A14W11
A15V11
BA0AA9
BA1AC7
BA2AB7
DDR3 PINFPGA PIN
D0U7
D1W3
D2U5
D3V4
D4U2
D5V6
D6U1
D7V3
D8W1
D9Y1
D10Y2
D11AA3
D12V1
D13AC2
D14V2
D15AB2
DDR3 PINFPGA PIN
D16AD6
D17AB4
D18AC6
D19Y6
D20AC3
D21Y5
D22AC4
D23AA4
D24AF3
D25AF2
D26AE3
D27AE2
D28AE6
D29AE1
D30AE5
D31AD1

MIG Settings

Kintex-7 devices support external, high-performance memory through the use of the Memory Interface Generator (MIG) provided by Xilinx. MIG produces a custom memory interface core that may be included in your design. These parameters have been used successfully within Opal Kelly but your design needs may require deviations.

All settings are based on MIG 2.3 (Rev. 1) and Vivado 2015.1.

PARAMETERXEM7360-K160T
Controller TypeDDR3 SDRAM
Clock Period1250ps (800.00MHz)
PHY to Controller Clock Ratio4:1
Vccaux_io2.0V
Memory TypeComponents
Memory PartMT41K512M8XX-125
Memory Voltage1.5V
Data Width32
ECCDisabled
Data MaskEnabled
OrderingNormal
Input Clock Period5000ps (200MHz)
Read Burst Type and LengthSequential – 8
Output Driver Impedance ControlRZQ/6
Controller Chip Select PinEnable
RTT (nominal) – On Die Termination (ODT)RZQ/6
Memory Address MappingBANK | ROW | COLUMN
System ClockDifferential
Reference ClockUse System Clock
System Reset PolarityActive High
Debug Signals for Memory ControllerOff
Internal VrefDisabled
IO Power ReductionOn
XADC InstantiationEnabled
Internal Termination Impedance40 Ohms
DCI CascadeDisabled
sys_clk_p/nAB11/AC11(CC_P/N)
Rtt WR – Dynamic ODTDynamic ODT off