Gigabit Transceivers

Access to eight high-speed serial transceiver pairs (8 Rx and 8 Tx) corresponding to GTX tiles 115 and 116 on the FPGA are available on the expansion connectors. MGTREFCLK0 of tile 115 and MGTREFCLK0 of tile 116 are also routed to expansion connectors. MGTREFCLK1 of tile 115 is connected to a low-jitter 100 MHz LVDS oscillator.


0.1μF AC-coupling capacitors are installed between the expansion connectors and the FPGA for all MGTREFCLK signals.

AC-coupling capacitors are not installed for any of the GTP transmit or receive pairs. If AC-coupling is desired or required for the serial application, they should be installed on the peripheral side (your board).

IBERT Configuration

Xilinx provides the IBERT tool to test and experiment with gigabit transceivers.  The settings below are compatible with the XEM7360 using Vivado 2015.1:

Silicon Version General ES / Production  
Protocol Custom 1  
Line Rate 8 Gbps  
Data Width 32  
Ref Clk 100.000 MHz  
Quad Count 1  
Quad PLL Checked  
GTX Location QUAD_115 QUAD_116
RefClk Selection MGTREFCLK1_115 MGTREFCLK0_116
TXUSRCLK Source Channel 0 Channel 0
Add RXOUTCLK Probes Unchecked  
Clock Type System Clock  
Source External  
I/O Standard LVDS  
P Package Pin AB11  
N Package Pin AC11  
Frequency 200 MHz  
Enable DIFF Term. Unchecked  

Gigabit Transceiver IBERT Performance

Xilinx’s IBERT tool enables an automated self-measurement of a GTP channel’s eye diagram when used in a loopback mode. Eye diagrams for three different speeds were captured using this tool with a simple loopback peripheral attached to the expansion headers. While results may vary, these are typical captures and actually represent the worst case capture over all channels for the respective rates.

Note that in loopback modes, it can be helpful to disable the GBT DFE (decision feedback equalizer) to avoid over-compensation. In these test cases, the DFE has been left enabled.

3.3 Gbps / XEM7360-K160T

6.6 Gbps / XEM7360-K160T

8.0 Gbps / XEM7360-K160T