BRK7360 Breakout Board
Unlike our integration modules, breakout boards are not intended for production integration. We reserve the right to change dimensions and functionality of this board at any time and may not necessarily have the previous version available for purchase.
IPMI EEPROM
The XEM7360 may optionally read peripheral information and configuration data from a small EEPROM on the peripheral. If available, the EEPROM can be used to automatically set the voltages for the three programmable voltage regulators on the XEM7360. An EEPROM is installed on the BRK7360 but is not loaded with any configuration. Use Opal Kelly’s IPMI EEPROM Generator Tool to generate an EEPROM image, then use FrontPanel’s Flash Programming Tool to download the image to the EEPROM.
Peripherals and Connectors
The table below summarizes the various connectors on the BRK7360. The XEM7360 Pin List has connection information in the “BRK7360” column. Additionally, please refer to the schematics and layout available online for detailed connection diagrams.
| CONNECTOR TYPE | REFDES | FPGA MGT QUAD | |
|---|---|---|---|
| U.FL | J12 – J15 | GTX115 | TxRx 0 |
| U.FL | J8 – J11 | GTX115 | TxRx 1 |
| SFP | J3 | GTX115 | TxRx 2 |
| SFP | J2 | GTX115 | TxRx 3 |
| SMA | J4 – J7 | GTX116 | TxRx 0 |
| SATA | J18 | GTX116 | TxRx 1 |
| SATA | J17 | GTX116 | TxRx 2 |
| SATA | J16 | GTX116 | TxRx 3 |
100-MHz Oscillator
The 100-MHz oscillator is provided as an alternate external reference for transceivers.
SFP Transceiver Sockets
The BRK7360 has two SFP cages installed, but the optical transceivers are optional. The following Finisar part is one example option.
| MANUFACTURER | PART NUMBER | DIGI-KEY P/N | APPROXIMATE COST |
|---|---|---|---|
| Finisar | FTLF8524P2BNV | 775-1045-ND | $53.55 / each |
Note: The polarity of the RX p/n pairs connected to the SFP transceiver connectors are swapped. To use the SFP transceiver ports the RXPOLARIY register must be set to 1 in the GTX configuration.
The following instructions describe this process in IBERT:
- Open the Vivado Hardware Manager and program the FPGA with the IBERT bitstream.
- In the “Hardware” view, under the IBERT dropdown, select the MGT channel you wish to use (for the J2 SFP cage this is MGT_X0Y3, for J3 this is MGT_X0Y2).
- Open the GT Properties pane in the view below the “Hardware” view used in the previous step.
- In the GT Properties pane, expand the “PORT” selection.
- Change the value of the “RXPOLARITY” register to 1.
- At this point everything should work as it normally would with IBERT. You should be able to create links, perform scans, etc.
Schematic and Design Files
The BRK7360 schematics and design files are available in the Downloads section of the Pins website.
Mechanical Drawing
