DDR3 Memory
The Micron DDR3 SDRAM is connected exclusively to the 1.5-v I/O on Banks 33 and 34 of the FPGA. The tables below list these connections.
The following resources are available to help provide guidance for designs that involve this memory:
- How-To Apply DDR MIG Settings and Vivado Board File to generate Xilinx’s MIG IP Core.
- The RAMTester sample reads and writes this memory via FrontPanel pipe endpoints.
- The XEM7360 Pins Reference can generate a constraints file (click on Export) with complete pin mapping and I/O constraints for use in your design.
Important VREF Note
The XEM7360 applies an external voltage reference to pins AD3 and W4 for applications using DDR3 memory. When the memory is not used in a design, these pins must set to high impedance. Not doing this can lead to contention between these multi-function IO pins and the VREF supply.
Connection Tables
| DDR3 PIN | FPGA PIN |
|---|---|
| RESET | AA2 |
| CKp | W10 |
| CKn | W9 |
| CKE | AC12 |
| CS | AB12 |
| RAS | AB9 |
| CAS | AC9 |
| WE | AD9 |
| DQS0p | W6 |
| DQS0n | W5 |
| DQS1p | AB1 |
| DQS1n | AC1 |
| DQS2p | AA5 |
| DQS2n | AB5 |
| DQS3p | AF5 |
| DQS3n | AF4 |
| DM0 | U6 |
| DM1 | Y3 |
| DM2 | AB6 |
| DM3 | AD4 |
| ODT | AA13 |
| DDR3 PIN | FPGA PIN |
|---|---|
| A0 | AD8 |
| A1 | AC8 |
| A2 | AA7 |
| A3 | AA8 |
| A4 | AF7 |
| A5 | AE7 |
| A6 | W8 |
| A7 | V9 |
| A8 | Y10 |
| A9 | Y11 |
| A10 | Y7 |
| A11 | Y8 |
| A12 | V7 |
| A13 | V8 |
| A14 | W11 |
| A15 | V11 |
| BA0 | AA9 |
| BA1 | AC7 |
| BA2 | AB7 |
| DDR3 PIN | FPGA PIN |
|---|---|
| D0 | U7 |
| D1 | W3 |
| D2 | U5 |
| D3 | V4 |
| D4 | U2 |
| D5 | V6 |
| D6 | U1 |
| D7 | V3 |
| D8 | W1 |
| D9 | Y1 |
| D10 | Y2 |
| D11 | AA3 |
| D12 | V1 |
| D13 | AC2 |
| D14 | V2 |
| D15 | AB2 |
| DDR3 PIN | FPGA PIN |
|---|---|
| D16 | AD6 |
| D17 | AB4 |
| D18 | AC6 |
| D19 | Y6 |
| D20 | AC3 |
| D21 | Y5 |
| D22 | AC4 |
| D23 | AA4 |
| D24 | AF3 |
| D25 | AF2 |
| D26 | AE3 |
| D27 | AE2 |
| D28 | AE6 |
| D29 | AE1 |
| D30 | AE5 |
| D31 | AD1 |
MIG Settings
Kintex-7 devices support external, high-performance memory through the use of the Memory Interface Generator (MIG) provided by Xilinx. MIG produces a custom memory interface core that may be included in your design. These parameters have been used successfully within Opal Kelly but your design needs may require deviations.
All settings are based on MIG 2.3 (Rev. 1) and Vivado 2015.1.
| PARAMETER | XEM7360-K160T |
|---|---|
| Controller Type | DDR3 SDRAM |
| Clock Period | 1250ps (800.00MHz) |
| PHY to Controller Clock Ratio | 4:1 |
| Vccaux_io | 2.0V |
| Memory Type | Components |
| Memory Part | MT41K512M8XX-125 |
| Memory Voltage | 1.5V |
| Data Width | 32 |
| ECC | Disabled |
| Data Mask | Enabled |
| Ordering | Normal |
| Input Clock Period | 5000ps (200MHz) |
| Read Burst Type and Length | Sequential – 8 |
| Output Driver Impedance Control | RZQ/6 |
| Controller Chip Select Pin | Enable |
| RTT (nominal) – On Die Termination (ODT) | RZQ/6 |
| Memory Address Mapping | BANK | ROW | COLUMN |
| System Clock | Differential |
| Reference Clock | Use System Clock |
| System Reset Polarity | Active High |
| Debug Signals for Memory Controller | Off |
| Internal Vref | Disabled |
| IO Power Reduction | On |
| XADC Instantiation | Enabled |
| Internal Termination Impedance | 40 Ohms |
| DCI Cascade | Disabled |
| sys_clk_p/n | AB11/AC11(CC_P/N) |
| Rtt WR – Dynamic ODT | Dynamic ODT off |