In addition to the transceivers available through SYZYGY Ports E and F on banks 224 and 225 respectively, one transceiver quad is used to support SMA connections and two SFP+ ports.

SFP1 and SFP2 transceiver signals are routed directly to Bank 226 transceivers. 0 Ohm series resistors are placed on the pairs.

SFP1 and SFP2 control pins are routed through level translators to FPGA Bank 87, an HD bank. This allows the 3.3V I/O on the SFP modules to be compatible with whichever voltage is selected for bank 87 by the SYZYGY peripheral at SYZYGY Port D.

After level translation, these signals are routed to FPGA pins as shown in the table below.

Six SMA connectors on the XEM8320 provide direct access to one transmit lane, one receive lane, and one reference clock on FPGA Bank 226.

0.1μF AC-coupling capacitors are installed between the SMA connectors and the FPGA for the MGTREFCLK1 P/N signals.

0.1μF AC-coupling capacitors are installed on the receive pairs. 0 Ohm series resistors are placed on the transmit pairs.

Along with the SMA reference clock connected to MGTREFCLK1, a 125 MHz fixed clock oscillator is connected to MGTREFCLK0 on Bank 226.

All transceiver differential signals on the XEM8320 are routed with 100Ω differential impedance and all pairs are length matched to within 5mils.