DDR3 Memory

The Micron DDR3 SDRAM is connected exclusively to the 1.5-v I/O on Banks 33 and 34 of the FPGA. The tables below list these connections.

The following resources are available to help provide guidance for designs that involve this memory:

Important VREF Note

The XEM7350 applies an external voltage reference to pins AD3, W4, AE11, and W8. for applications using DDR3 memory. When the memory is not used in a design, these pins must set to high impedance. Not doing this can lead to contention between these multi-function IO pins and the VREF supply.

Connection Tables

DDR3 PINFPGA PIN
RESETnAA4
CKpW6
CKnW5
CKEAB5
CSnAA5
RASnAC2
CASnAA3
WEnAA2
DQS0pAF5
DQS0nAF4
DQS1pW10
DQS1nW9
DM0AD4
DM1V11
ODTAB6
DDR3 PINFPGA PIN
A0AC1
A1AB1
A2V1
A3V2
A4Y2
A5Y3
A6V4
A7V6
A8U7
A9W3
A10V3
A11U1
A12U2
A13U5
A14U6
BA0AB2
BA1Y1
BA2W1
DDR3 PINFPGA PIN
D0AD1
D1AE1
D2AE3
D3AE2
D4AE6
D5AE5
D6AF3
D7AF2
D8W11
D9V8
D10V7
D11Y8
D12Y7
D13Y11
D14Y10
D15V9

MIG Settings

Kintex-7 devices support external, high-performance memory through the use of the Memory Interface Generator (MIG) provided by Xilinx. MIG produces a custom memory interface core that may be included in your design. These parameters have been used successfully within Opal Kelly but your design needs may require deviations.

PARAMETERXEM7350-K70TXEM7350-K160T
System Clock TypeDifferential
Reference Clock TypeUse System Clock
System Reset PolarityActive High
Debug PortOff
Internal VrefDisabled
IO Power ReductionOn
DCI for DQ / DQS / DMEnabled
Internal Termination40 Ω
MemoryDDR3_SDRAM
InterfaceNative
Design Clock Frequency2500ps (400.0 MHz)1250ps (800.0 MHz)
Phy to Controller Ratio4:14:1
Input Clock Period5000ps5000ps
CLKFBOUT_MULT48
DIVCLK_DIVIDE1
Vcc_aux_io2.0V
Memory TypeComponents
Memory PartMT41K256M16XX-125
Data Width16
ECCDisabled
Data MaskEnabled
OrderingNormal
Burst Length8 – Fixed
Read Burst TypeSequential
CAS Latency611
Output Drive StrengthRZQ/6
Controller CS OptionEnable
Rtt NOM – ODTRZQ/6
Rtt WR – Dynamic ODTDynamic ODT off
Memory Address MappingBANK_ROW_COLUMN
Bank 33Byte Group T0 : DQ[8-15]
Bank 34Byte Group T0 : Address/Ctrl-0
Byte Group T1 : Address/Ctrl-1
Byte Group T2 : Address/Ctrl-2
Byte Group T3 : DQ[0-7]
sys_clk_p/nAC4/AC3