Opal Kelly Pins is an interactive online reference for the expansion connectors on all Opal Kelly FPGA integration modules. It provides additional information on pin capabilities, pin characteristics, and PCB routing.
Pins can also generate constraint files (XDC) and help you map your HDL net names to FPGA pin locations automatically.
The Pins reference for the XEM7350 may be found at the link to the right.
FMC Expansion Connector
FMC (FPGA Mezzanine Connector) is the common name for the VITA 57 specification which describes a common connector design to interface large pin-counts to devices with configurable I/O such as an FPGA. The specification is available for purchase through the VITA website:
The XEM7350 specifically supports the HPC (high pin-count) version of the specification (Note: the -K70T does not have a fully-populated HPC connector). For details on supported FMC features, please see the FMC Feature Support section. FMC connectors are manufactured by Samtec. The FMC connector on the XEM7350 is the Samtec ASP-134486-01. The mating connector which would appear on an FMC peripheral is the Samtec ASP-134488-01. These are both surface-mount pin-field-array style connectors. The connectors ship with a solder plug on each connector which melts during reflow to the solder paste spread on the bare board for assembly. Connector contact is solid and insertion and removal forces are relatively small. High frequency performance is up to 9.5 GHz in single-ended operation and to 10.5 GHz in differential operation.
Fan Power Supply
A small 2-pin connector (Molex 53398-0271) at JP1 provides power to an optional fan for FPGA cooling. This fan is under direct or temperature-proportional control of a digital fan controller. Please see the Device Settings section for details on controlling the fan.
A single FMC-HPC (high pin count) connector provides direct access to I/O pins and Gigabit transceiver on the FPGA. The tables below illustrate the number of pins that are available on an FMC-HPC connector and the number that are routed to available sites on the FPGA.
|BANK / GROUP (I/O VOLTAGE)||FMC-HPC||-70T||-160T/-410T|
|LA (Vadj) – I/O pairs||34||34||34|
|HA (Vadj) – I/O pairs||24||0||24|
|HB (Vio) – I/O pairs||22||0||22|
|GBT – # of transceivers||10||8||8|
Clock pins are given special attribution within the FMC specification. Available clock pins are illustrated in the table below.
|BANK / GROUP (I/O VOLTAGE)||FMC-HPC||-70T||-160T/-410T|
|LA (Vadj) – Clock pairs||2||2||2|
|HA (Vadj) – Clock pairs||1||1||1|
|HB (Vio) – Clock pairs||1||0||1|
|GBT – Reference Clocks||2||2||2|
FMC 12P0V Supply Pins
The XEM7350 does not supply the +12 VDC to the FMC expansion connector. If this is required for the peripheral, you may provide +12VDC through TP3 on the XEM7350. If you do this, please confirm that R48 is not inserted. Per the power supply diagram, this resistor connects the 12P0V pins on the FMC connector (C35 and C37) to the +5VDC input. This is not typically desired. By default, R48 is not inserted at the factory.
Setting the FMC Vadj I/O Voltage (LA and HA Groups)
FMC specifies a single adjustable voltage (Vadj) for the two LA groups that are routed to FPGA banks 15 and 16 and the HA group routed to FPGA bank 12. A high-efficiency switching regulator on the XEM7350 controls this voltage and is configured according to Device Settings
|0||Vadj output is disabled.|
|1||The contents of the IPMI EEPROM are queried. If the contents are valid, Vadj is set to the voltage specified. If the contents are not valid, then the voltage output is disabled.|
|2 (default)||The contents of the IPMI EEPROM on the FMC peripheral are queried. If the contents are valid, Vadj is set to the voltage specified. If the contents are not valid, then Vadj is set to the FMC1_VADJ_VOLTAGE as a fallback.|
|3||The contents of the IPMI EEPROM are ignored and Vadj is set to the value in FMC1_VADJ_VOLTAGE.|
Valid output voltages are: 3.3v, 2.5v, 1.8v, 1.5v, 1.25v, and 1.2v.
FMC / VITA 57.1 specifies that an I2C EEPROM shall be provided on the peripheral to store information about the peripheral module. The carrier (XEM7350) will read this information on boot and can set the Vadj settings above accordingly. Furthermore, this EEPROM shall be connected so that it recognizes the geographical address provided by the carrier for proper addressing of the EEPROM.
The implications of these requirements on your peripheral design are rather simple:
- Install an EEPROM on your board. We suggest using the Microchip 24LC64-I/SN or equivalent.
- Connect it according to the table below. Note the order of the EEPROM pin numbers and the geographical address as it is reversed from what you may expect.
|FMC PIN||FUNCTION||EEPROM PIN|
FMC Vio (HB Group)
The pins on the FMC HB group are routed to FPGA bank 32. Vcco for this bank is connected to FMC_VIO_B_M2C which is a voltage provided by the mezzanine (peripheral) to the carrier (XEM7350). Please see the Xilinx Kintex-7 User’s Manual for details on acceptable voltages.
The Xilinx Kintex-7 XADC feature is routed through two resistors to the FMC connector. In the factory configuration, these two resistors are not inserted. In the FMC specification, B24 and B25 locations are transceiver pin locations. These pins are otherwise not used on the XEM7350.
|FPGA FUNCTION||FPGA PIN||FMC||RESISTOR REFDES|
Considerations for Differential Signals
The XEM7350 PCB layout and routing has been designed with several applications in mind, including applications requiring the use of differential (LVDS) pairs. Please refer to the Xilinx Kintex-7 datasheet for details on using differential I/O standards with the Kintex-7 FPGA.
FPGA I/O Bank Voltages
In order to use differential I/O standards with the Kintex-7, you must set the VCCO voltages for the appropriate banks to 2.5v according to the Xilinx Kintex-7 datasheet. Please see the section above entitled “Setting the FMC Vadj I/O Voltage” for details.
The characteristic impedance of all routes from the FPGA to the expansion connector is approximately 50Ω.
Differential Pair Lengths
In many cases, it is desirable that the route lengths of a differential pair be matched within some specification. Care has been taken to route differential pairs on the FPGA to adjacent pins on the expansion connectors whenever possible. We have also included the lengths of the board routes for these connections to help you equalize lengths in your final application. Due to space constraints, some pairs are better matched than others.
Reference Voltage Pins (Vref)
The Xilinx Kintex-7 supports both internal and externally-applied input voltage thresholds for some input signal standards. The XEM7350 supports these Vref applications for banks 12, 15, 16, and 32. Please see the Xilinx Kintex 7 documentation for more details. In summary,
For banks 15 and 16, the four Vref pins are routed to the FMC connector pin VREF_A_M2C at location H1. Internal Vref may also be used.
For bank 12, internal Vref may be used. Vref pins are also available on the FMC connector pins HA18_N (J19) and HA22_N (J22) if external Vref is required. Doing so prevents the use of HA18_N and HA22_N for I/O.
For bank 32, internal Vref may be used. Vref pins are also available on the FMC connector pin VREF_B_M2C (K1). For external Vref you must install 0 Ω resistors (0402 dimension) at R105 and R106. Doing so prevents the use of HB01_N (J25) for I/O.
I/O State at Power On
Xilinx Kintex-7 FPGAs support a weak pull-up state on SelectIO pins after power-up and during configuration. This behavior is controlled by the PUDC_B pin.
The default PUDC_B configuration on the XEM7350 depends on the PCB revision.
- On PCB revisions FXX and later, the PUDC_B pin is pulled high by default to disable internal pull-up resistors at startup.
- On PCB revisions EXX and earlier, the PUDC_B pin is pulled low by default to enable internal pull-up resistors at startup.
To change the default behavior of your module, see the PUDC_B Configuration support page.