Sanitization procedures are intended to return the board to new condition and remove data that may have been programmed to non-volatile storage. These procedures are often performed when removing products from confidential areas.
Note that these procedures only cover removal of data from storage accessible by supported means. We don’t support sanitization of data written by undocumented methods.
The XEM7350 USB 3.0 firmware does not store any logs on the attached NVRAM.
|MEMORY||REF DES||MANUFACTURE P/N||DESCRIPTION / COMMENT|
|FX3 Firmware||U24||24FC256-I/SN||32 kB I2C EEPROM|
USB 3.0 first stage firmware
|System Flash||U27||S25FS128||128 Mb SPI Flash|
Flash available to FX3 for configuration boot and user storage
|FPGA Flash||U17||MT25QL128||128 Mb SPI Flash|
Flash available to FPGA for user storage
FX3 Firmware (I2C)
The firmware itself is not accessible by supported means and is therefore outside the scope of these sanitization procedures. If you are concerned about the contents of this section, you should purchase a new board and destroy the “dirty” board.
The XEM7350 System Flash has only three user-accessible areas:
- Device ID String – This is a short string used to identify each board. This can be written using the FrontPanel Application or the FrontPanel API
- Reset Profiles – The reset profile stores information used to configure the FPGA and FrontPanel interfaces at startup or when the FPGA is reconfigured through JTAG. This memory can be written to and cleared through the FrontPanel Application or the
- User Storage – Flash sectors 16 to 256 are available to the user for data storage. This memory can be cleared using the Flash Programming Tool or the
The FPGA flash may be reprogrammed by writing an appropriate file to the flash using the Flash Programming Tool in the FrontPanel Application. You can select “erase all” to erase the flash. If you need to overwrite the contents, you will need to generate a binary image to write to this flash.
Alternatively, you can write to this flash from the FPGA. You will need to design and configure the FPGA with appropriate logic to do this. Opal Kelly does not provide any example HDL to do this.