The Micron DDR3 SDRAM is connected exclusively to the 1.5-v I/O on Banks 33 and 34 of the FPGA. The tables below list these connections.

The following resources are available to help provide guidance for designs that involve this memory:

• How-To Apply DDR MIG Settings and Vivado Board File to generate Xilinx’s MIG IP Core.
• The RAMTester sample reads and writes this memory via FrontPanel pipe endpoints.
• The Camera Reference Design provides a memory interface for frame buffering.
• The XEM7350 Pins Reference can generate a constraints file (click on Export) with complete pin mapping and I/O constraints for use in your design.

Kintex-7 devices support external, high-performance memory through the use of the Memory Interface Generator (MIG) provided by Xilinx. MIG produces a custom memory interface core that may be included in your design. These parameters have been used successfully within Opal Kelly but your design needs may require deviations.