The PUDC_B pin on the Kintex-7 FPGA configures internal pullup resistors on the SelectIO pins after power-up and during configuration.

• When PUDC_B is low, internal pull-up resistors are enabled on each SelectIO pin.
• When PUDC_B is high, internal pull-up resistors are disabled on each SelectIO pin.

See Xilinx UG470 “7-Series FPGAs Configuration” for more information.

On the XEM7360, the PUDC_B pin has a configurable pull-up and pull-down resistor.

On PCB revisions EXX and later, the PUDC_B pin is pulled high by default to disable internal pull-up resistors at startup. To enable internal pull-ups, remove R66 and place a 1k resistor at R68.

On PCB revisions DXX and earlier, the PUDC_B pin is pulled low by default to enable internal pull-up resistors at startup. To disable internal pull-ups, remove R68 and place a 1k resistor at R66.

These resistors are located on the bottom side of the PCB (opposite of the FPGA) in the location shown below.