This reference is provided to help guide you through the design process of a mating peripheral to the XEM7310. It is not intended to be a comprehensive instruction manual. While we put forth great effort to reduce the effort required to build an FPGA-enabled platform, there are hundreds of pages of product documentation from Xilinx that should be considered. Use this guide as a roadmap and starting point for your design effort.

• XEM7360 Specifications
• BRK7360 Breakout Board
• Samtec QTH product page
• Samtec QTH data sheet
• Xilinx Power Estimator

Input power to the XEM7360 may be applied either through the DC barrel jack or through mezzanine header MC2. For information on the barrel jack dimensions and polarity, see Powering the XEM7360. For information on mezzanine header pin assignments, see the XEM7360 Pins Reference.

The total operating power budget is an important system consideration. The power budget for the XEM7360 is highly dependent on the FPGA’s operating parameters and this can only be determined in the context of an actual target design.

The onboard XEM7360 power supply regulators provide power for all on-board systems, including the VIO rails provided to the mezzanine headers. The Power Budget table on the Powering the XEM7360 page indicates the total current available for each supply rail. This table may be used to estimate the total amount of input power required for your design.

The XEM7360 applies an external voltage reference to pins AD3 and W4 for applications using DDR3 memory. When the memory is not used in a design, these pins must set to high impedance. Not doing this can lead to contention between these multi-function IO pins and the VREF supply.

Details on the available standards can be found in the following Xilinx documentation:

• Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS182)
• 7 Series FPGAs SelectIO Resources (UG471)

Voltage supply rails VADJ1, VADJ2, and VADJ3 power the FPGA I/O banks on mezzanine connectors MC1 and MC2. For information on configuring these voltages using FrontPanel, see the Device Settings page. See the XEM7360 Pins Reference for details about FPGA bank power assignments.

Refer to the XEM7360 mating board diagram for placement locations of the mezzanine connectors (Samtec QTH series) and mounting holes. This diagram can be found on the Specifications page of the XEM7360 documentation.

For recommended PCB layout of the Samtec QTH connector, refer to the QTH footprint drawing.

Refer to the XEM7360 Specifications for a comprehensive mechanical drawing. Also refer to the BRK7360 as a reference platform. The BRK7360 design files can be found in the Downloads section of the Pins website.

Refer to the XEM7360 mechanical drawing for locations of the USB jacks and the DC power jack. This drawing is available on the Specifications page of the XEM7360 documentation.

Thermal dissipation for the XEM7360 is highly dependent on the FPGA’s operating parameters and this can only be determined in the context of an actual target design.

An active FPGA cooling solution is recommended for any design with high power consumption. Opal Kelly provides an optional fansink designed to clip onto the XEM7360. See the Powering the XEM7360 page for more information. Some designs may require a different cooling solution. Thermal analysis and simulation may be required.

The Samtec QSH-series connectors on the XEM7360 mate with QTH-series connectors on the carrier board. The QTH series is available in several stacking height options from 5 to 30 mm. The stack height is determined by the “lead style” of the QTH connector.

Note that increased stack height can lead to decreased high-speed channel performance. Information on 3-dB insertion loss point is available on the Samtec website.