The SZG-HUB1450 provides three SYZYGY Standard ports to connect a variety of SYZYGY peripherals.

Refer to the SZG-HUB1450 Pins Reference for pin-level I/O bank assignments for each SYZYGY port.

Two software controlled DC-DC regulators power the two SYZYGY SmartVIO groups as assigned above. The behavior of these power supplies is determined by the HUB1450_SMARTVIO_MODE parameter in Device Settings and associated settings. The modes function as described below.

Note that, for modes that require a SmartVIO solution, if any peripheral provides non-compliant DNA, a SmartVIO solution cannot be reached for all groups.

• SmartVIO only – SmartVIO is tested collectively so all present SmartVIO peripherals must result in a collective validation for any of the outputs to be enabled.
• SmartVIO hybrid mode – Each group is individually tested for SYZYGY peripherals. Within each group, if a SYZYGY peripheral is present (via detection of compliant DNA data) on any of the ports within that group, the SmartVIO solution is used to determine the voltage setting. If no SYZYGY peripherals are detected within the group, then the corresponding Device Setting (e.g. HUB1450_VIO1_VOLTAGE) is used.
• Device Settings only – SmartVIO settings from the peripherals are ignored, only the device settings are used. Also note that, in this mode, SYZYGY peripheral discovery is not performed so the corresponding device settings that identify each peripheral are not populated.

The SmartVIO solution for each group is determined by the voltage range(s) supported by the corresponding FPGA I/O banks and the voltage range(s) supported by the peripherals, as reported in their respective SYZYGY DNA. The process is as follows:

1. The SmartVIO controller (SZG-HUB1450) queries all detected peripherals for their SYZYGY DNA.
2. The controller attempts to determine the lowest voltage that will satisfy all attached peripherals and FPGA ranges.
3. If a solution is not found, the group voltage remains disabled to protect any incompatible devices on the group.
4. If a solution is found, the group voltage is set to the voltage and enabled.

Peripherals that use LVDS may have a fixed or limited voltage range depending on the carrier. LVDS usage is stored as a flag in the peripherals SYZYGY DNA. Commonly this will limit the SmartVIO solution to 1.8V or 2.5V depending on the I/O bank type connected to the SYZYGY port (as with the SZG-HUB1450), but other voltages may be set depending on the specific FPGA requirements.

The SYZYGY power rails current output is limited by the regulator used on the carrier as well as the current carrying capacity of the SYZYGY connector. The onboard regulator limits are listed on each carriers SYZYGY Compatibility Table (see below) which shows the total current output maximum for all of the ports combined. Each individual port is limited to 2A output for each of the 3 SZYGY power rails (3.3V, 5V, and VIO) by the current carrying capacity of the SYZYGY connector.

SYZYGY port A is connected to HP Bank 64 and HD Bank 84. The VRP pin on Bank 64 (IO_T0U_N12_VRP_64) is connected to ground through a 240 ohm resistor. This is a requirement to use certain high performance IOSTANDARDs.

High performance IOSTANDARDs that utilize VRP pins typically require strict placement of data and clock within the same IO byte group of a bank. Using the SZG-HUB1450 Pins Reference paired with the AU10P FFVB676 Package Device Pinout file, you’ll be able to make a correlation between the SYZYGY connector pin and the associated AMD full pin name, i.e., IO_L7N_T1L_N1_QBC_AD13N_64. Definitions of the various identifiers within the full name are at UltraScale+ Device Packaging and Pinouts Product Specification User Guide (UG575).

The SZG-MIPI-8320 is an example of a peripheral that utilizes VRP pins as part of the MIPI_DPHY_DCI IOSTANDARD. The SZG-MIPI-8320’s documentation discusses this in more detail.

The SZG-HUB1450 PCB layout and routing has been designed with several applications in mind, including applications requiring the use of differential (LVDS) pairs. Please refer to the Artix UltraScale+ datasheet for details on using differential I/O standards with the Artix UltraScale+ FPGA.

Single-ended SYZYGY signals are routed to the FPGA with 50Ω characteristic impedance. Differential SYZYGY signals are routed to the FPGA as trace pairs with 100Ω differential impedance. Pin/package delay information may be obtained from the AMD design tools. The additional notes below also apply.

• SYZYGY I/O is routed directly from the SYZYGY connector to the FPGA with no circuitry in between, except for optional differential input termination resistors on LVDS pairs connected to FPGA banks 85 and 86. (See “FPGA Differential I/O Standards” below.)
• All clock and data routes between the FPGA and a SYZYGY connector (within the same port) are matched to within 5 mils (0.13 mm). This matching includes the pin/package delays of the Artix UltraScale+. Ports are not matched to each other.
• The length matching numbers in the compatibility tables below represent routed PCB lengths only and do not include the pin/package delays.
• Individual PCB routing lengths for all SYZYGY I/O is available on the SZG-HUB1450 Pins Reference page. The lengths published there represent routed PCB lengths only and do not include the pin/package delays.

The different I/O banks on the Artix UltraScale+ have different features and specific requirements needed to use differential I/O standards.

HP banks support LVDS inputs and outputs. The bank VCCO must be set to 1.8V to use LVDS outputs. This also allows the use of the available internal termination on LVDS inputs.

HD banks only support LVDS inputs, and only with external termination. The SZG-HUB1450 provides optional external termination resistor positions near the FPGA. These termination resistors are unpopulated by default to avoid interfering with single-ended connections. See the diagram below for resistor locations, identified in yellow.

The bank type associated with each SYZYGY port is listed in the Port Summary above.

Please see LVDS Interface Checklist for more information. Also see AMD DS931 for information regarding the LVDS DC Specifications on the Artix UltraScale+. For more information on the differential I/O standard limitations of HD banks see the “High Density I/O Resources” section of AMD UG571.

SYZYGY peripherals can be mechanically connected together using the carrier and peripheral mounting holes. Below are some suggested mounting hardware options. The Standard Hardware mounting kit is available from the accessories section of our store.

Notes:

1. The differential I/O on Port C supports LVDS input only due to limitations of HD banks on the Artix UltraScale+ FPGA. External termination resistors must be populated.