The 1-GiByte DDR4 SDRAM provides a 16-bit wide data interface and is connected exclusively to HP Bank 66 of the FPGA. The maximum data rate of the SDRAM interface of the -1 speed grade Artix UltraScale+ (single rank component) is limited to 2133 Mb/s. This gives a supported peak memory bandwidth of 34.128 Gb/s.

The following resources are available to help provide guidance for designs that involve this memory:

• How-To Apply DDR MIG Settings and Vivado Board File to generate AMD’s MIG IP Core.
• The RAMTester sample reads and writes this memory via FrontPanel endpoints.
• The Camera Reference Design provides a memory interface for frame buffering.
• The SZG-HUB1450 Pins Reference can generate a constraints file (click on Export) with complete pin mapping and I/O constraints for use in your design.

Artix UltraScale+ devices support external, high-performance memory through the use of the Memory Interface Generator (MIG) provided by AMD. MIG produces a custom memory interface core that may be included in your design. These parameters have been used successfully within Opal Kelly but your design needs may require deviations.

All settings are based on the DDR4 SDRAM (MIG) v2.2 IP and Vivado 2025.2. This configuration sets up the correct MMCM M/D values to use an exact 156.25-MHz reference input clock to achieve exactly 2166 Mb/s performance. This is a contradiction to the GUI reported 156.779MHz for the selection of “6379” for “Reference Input Clock Speed (ps).” Please see AMD Article 66554 for more information regarding a similar situation.

The FPGA to DDR4 pin mappings are shown below. These are also available in the Pins Reference when exporting a constraints file as well as the sample designs that utilize the memory.