Flash Memory
Shared Flash
The SZG-HUB1450 has a single on-board flash part for both application data and power-on FPGA configuration data.
The SZG-HUB1450’s on-board flash is a 256 Mbit serial flash. Erase, read, and write functions are available at all times (with or without a configured FPGA) through the use of FrontPanel API methods. Flash data, such as calibration settings, can be passed to the FPGA via the API.
Layout
The flash (ISSI IS25WP256E-JLLE or similar) is a 256 Mbit flash memory arranged into 512x 65,536 byte (64 KiB) blocks. Each block contains 16x 4,096 byte (4 KiB) sectors. Each sector contains 16x 256 byte pages. The entire flash may be erased, written, and read using the FrontPanel API at any time even without a valid FPGA configuration. Full 64 KiB blocks must be erased at a time. However, contents may be read or written on any page address boundary.
Power-on FPGA configuration data must be stored at the start of the flash space. When power-on configuration data is loaded into the flash, unused flash blocks at the end of the flash space can still be used for application data non-volatile storage.
Flash Connection
The flash memory is connected to the FPGA configuration bank (Bank 0). The STARTUPE3 AMD primitive is utilized by the FrontPanel Host Interface and not available directly in user designs. Non-volatile application data, such as calibration parameters, can be read from flash by the host via the FrontPanel API, and transferred to the FPGA via the API.
The on-board flash is on a shared bus and should not be accessed directly by the FPGA even when FrontPanel is not used. If direct flash access from the FPGA is required, a flash part must be connected to one of the SYZYGY ports.
Flash API Access
The API includes three methods for accessing the on-board flash memory: FlashEraseSector, FlashWrite, and FlashRead. Please refer to the FrontPanel API Reference for information about applying these methods.
Loading a Power-On FPGA Configuration
The flash may be used to store a bitfile to configure the FPGA at power-on. The flash can be written using the FrontPanel Application, the FrontPanel API or through Vivado with a JTAG cable. An FPGA configuration loaded in the flash will always load at power-on until the flash memory containing the configuration is erased.
An active JTAG connection interferes with power-on configuration. Remove any JTAG adapter connections before testing power-on configuration.
XDC Constraints for FPGA Flash Configuration
If you plan to utilize the flash for configuring the FPGA at power-on, the Vivado software needs certain details about the flash to generate a suitable bitfile for this specific configuration mode. This bitfile is subsequently loaded into the flash. To accomplish this, implement the following XDC constraints within your project.
It is important to understand that if you generate bitfiles with the following constraints, they cannot be loaded through the FPGA Configuration Download feature in the FrontPanel application. Trying to do so will result in an error message stating FPGA configuration failed: Done did not go high.
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design]Code language: Verilog (verilog)