JTAG on FPGA Bank 0 may be accessed through a set of six test points located between the FPGA and SYZYGY port B. The test point arrangement is compatible with Tag-Connect connectors and cables.

The compatible Tag-Connect interface components are listed in the table below.

To provide tool access to JTAG, a vendor-supported JTAG programming cable is required. The JTAG cables listed below are compatible with the Tag-Connect interface components listed above.

The FPGAs XADC pins are not available for use on the SZG-HUB1450.

The SYSMON sensor data for FPGA temperature, VCCINT voltage, VCCBRAM voltage, and VCCUAX voltage can be provided as device sensors in FrontPanel, as long as the FPGA is configured with a bitfile that instantiates the SYSMON privative. The FrontPanel host interface comes with the SYSMON privative correctly instantiated by default, but this can be disabled with the OMIT_SYSMON okHost parameter.

// By default, sysmon is included when instantiating okHost:
okHost okHost_i (
    ....
);

// To omit sysmon, set the OMIT_SYSMON parameter to 1:
okHost #(
    .OMIT_SYSMON(1)
) okHost_i (
    ....
);Code language: Verilog (verilog)

To instantiate the SYSMON privative in your own HDL and still use the SYSMON sensors in FrontPanel device sensors, use this example.

SYSMONE4 #(
    .INIT_43(16'b1_1011011_0_000_0000)
) SYSMONE4_inst (
    .I2C_SCLK_TS(i2c_sclk_ts),
    .I2C_SDA_TS(i2c_sda_ts),
    .I2C_SCLK(i2c_sclk_in),
    .I2C_SDA(i2c_sda_in)
);Code language: Verilog (verilog)

The FrontPanel device sensors SYSMON instantiation must use these I2C pins, and be set to device address 0x5B (1011 011x).