Device Settings
The SZG-HUB1450 supports the FrontPanel Device Settings in the table below, accessible from the FrontPanel Application as well as the Device Settings API.
SZG-HUB1450 Device Settings
The SZG-HUB1450 has three standard SYZYGY ports that support SmartVIO for automatic interface voltage selection. These settings may optionally be overridden by the settings below.
See the SYZYGY Ports page for more information on device settings VIO control and SmartVIO operation.
| NAME | TYPE | DESCRIPTION |
|---|---|---|
| HUB1450_VIO1_VOLTAGE | INT32 | VIO1 output voltage specified in 10’s of mV. For example, “180” would set VIO1 = 1.8v. Supports any value from 120 to 180 as well as 0 (default). |
| HUB1450_VIO2_VOLTAGE | INT32 | VIO2 output voltage specified in 10’s of mV. For example, “330” would set VIO2 = 3.3v. Supports any value from 120 to 330 as well as 0 (default). |
| HUB1450_SMARTVIO_MODE | INT32 | Register used to control the behavior of the SmartVIO solver on the XEM8320. See SYZYGY Ports documentation for additional information on these modes. 0x00 – SmartVIO only (default) – SmartVIO is used to calculate a VIO voltage that supports all present SmartVIO peripherals. It must find a valid solution for all peripherals in a VIO group for that output rail to be enabled. The lowest voltage that is acceptable to all connected peripherals is used. 0x01 – SmartVIO with Device Settings fallback – If any SmartVIO peripherals are present on the VIO group, then the SmartVIO solution will be used to set the VIO rail voltage. If no SmartVIO peripherals are present, then use the Device Settings configured voltage value. 0x02 – Device Settings only – Always use the Device Settings configured voltage. Ignore SmartVIO solutions. Use with caution |
| HUB1450_FAN_MODE | INT32 | 0=Binary mode (default) 1=Temperature controlled mode Temperature based control only works with instantiated SYSMON |
| HUB1450_FAN_ENABLE | INT32 | Fan control in binary mode. 0=Disable 1=Enable (default) |
| HUB1450_FAN_TEMP_THRESHOLD | INT32 | In temperature controlled mode, the number here represents the threshold (in degrees Celsius) for fan enable (default 16C). This is the FPGA internal die temperature. At THRESH, fan is enabled At THRESH-10C, fan is disabled |
SYZYGY Device Discovery
The following settings are common to all FrontPanel devices that support SYZYGY either natively or through a compatible breakout board or reference platform.
The SZG-HUB1450 has three ports, supporting n=0...2. SYZYGY port mapping can be found in the Port Summary table.
| NAME | TYPE | DESCRIPTION |
|---|---|---|
| SYZYGYn_PORT_STATUS | INT32 | Indicates the selected voltage for this port in 10’s of mV. For example, “330” means that the SmartVIO solution is 3.3V. If a solution was not found, this will read “0” and the port will be unpowered. |
| SYZYGYn_MANUFACTURER_NAME | STRING | The peripheral’s manufacturer name as reported by its SYZYGY DNA. |
| SYZYGYn_PRODUCT_NAME | STRING | The peripheral’s manufacturer name as reported by its SYZYGY DNA. |
| SYZYGYn_PRODUCT_MODEL | STRING | The peripheral’s product model as reported by its SYZYGY DNA. |
| SYZYGYn_PRODUCT_VERSION | STRING | The peripheral’s product version as reported by its SYZYGY DNA. |
| SYZYGYn_SERIAL_NUMBER | STRING | The peripheral’s serial number as reported by its SYZYGY DNA. |
SYZYGY SmartVIO
In SYZYGY SmartVIO mode the VIO voltage is determined by first reading the SYZYGY DNA of all SYZYGY peripherals then solving for a SmartVIO solution. The lowest voltage that is acceptable to all connected peripherals will be used. On the SZG-HUB1450, ports A and B correspond to VIO group 1, and port C corresponds to VIO group 2. SYZYGY port and VIO rail mappings can be found in the Port Summary table. The SYZYGY port ID is determined by the port’s geographical address resistor as specified in the SYZYGY DNA Specification. When HUB1450_VIO_MODE is set to 0x00, all ports are scanned for peripherals which are then entered into the SmartVIO solver to determine what VIO voltage will be set.
Fan Control Device Settings
To use the fan control device settings, a fansink must be connected to the 2-pin connector labeled “FAN”. See Specifications for more information on compatible fansinks.
For most applications, we recommend binary operating mode with the fan enabled at all times. You may optionally configure an FPGA die temperature threshold at which to automatically enable the fan.