The SZG-HUB1450 is a bus-powered USB device. Power may be provided directly by the host PC or through the optional dedicated power connector. An onboard eFuse with automatic current limit adjustment provides overcurrent protection of the USB supply as well as overvoltage protection of the SZG-HUB1450.

The SZG-HUB1450 power distribution system comprises a USB power manager, voltage regulators for system and peripheral supplies, load switches, and voltage/current sensors for monitoring power usage. The voltage regulators include several high-efficiency DC-DC switching regulators and low-noise linear regulators. A block diagram of the power distribution system is shown below.

The USB power manager configures the power path automatically according to the capabilities of the available USB supplies. Power is provided to the device in one of two ways:

1. From a USB host connected to the “HOST” USB-C connector
2. From a USB Power Delivery compatible supply connected to the “POWER” USB-C connector

The POWER input has a higher priority than the HOST input. When both inputs are connected to valid supplies, the USB power manager will automatically switch to the POWER input. The inputs may be attached or detached in any order. The POWER input may be attached during operation while the HOST input is connected, although this may potentially cause a board reset as the power manager transitions between sources.

USB hosts (data ports on personal computers) are typically capable of providing power to connected devices. This allows the convenience of single-cable operation (shared data and power) when the available power from the host supports the SZG-HUB1450 power requirement.

A USB-C host typically provides one of the following current levels, collectively known as “Type-C Current”. The current level is advertised by the host to the device using the Channel Configuration (CC) pins of the USB-C cable. The SZG-HUB1450 USB power manager detects the advertised current level and adjusts the onboard eFuse current limit accordingly. Type-C Current is always provided at +5 VDC nominal voltage. The current and power levels in the table represent the maximum levels the device is allowed to draw in each mode.

The optional POWER input can be used to power the SZG-HUB1450 when there is insufficient power available through the HOST input, or when current draw from the host must be restricted. When used, the POWER input must be connected to a USB Power Delivery (PD) compliant supply. Examples of this type of supply include standalone USB-C chargers and power supplies, and dedicated charging ports on PCs. The vast majority of standalone USB-C supplies are PD-compliant, making the SZG-HUB1450 broadly compatible with commercially available supplies. The POWER input is not generally compatible with data ports on PCs because these do not typically include PD capability.

When connected to a USB PD supply, the SZG-HUB1450 attempts to negotiate a compatible power level with the supply. The supply must be capable of providing least 1.0 A output current at 9 V or 15 V. The SZG-HUB1450 will request the maximum current provided by the supply (up to 3.0 A) at the maximum compatible voltage. If there is no match between the supply capabilities and the requested power levels, the SZG-HUB1450 will not use any power from the PD supply. The table below lists the minimum and maximum requested power levels. Intermediate current values between 1.0 and 3.0 A are possible. PD supplies capable of maximum voltages or power levels greater than shown in the table are compatible as long as they provide at least one of the levels within these ranges.

When operating from a compatible USB PD supply, the onboard eFuse is configured for a current limit of 3.0 A, independent of the negotiated power level. It is up to the user to connect a supply capable of supporting the power needs of the SZG-HUB1450 application.

The SZG-HUB1450 includes several LED indicators for power status.

A red PWR LED indicates a power fault. This indication is given only when power is being sourced through the POWER input. There are two conditions which cause a power fault:

1. eFuse over-current protection engaged — As current through the eFuse begins to exceed the over-current protection threshold, the eFuse attempts to limit its output current by dropping the output voltage. The extraneous power is dissipated as heat in the eFuse. As long as the eFuse output voltage remains in a valid range for the onboard voltage regulators and the over-temperature threshold is not reached, the eFuse remains connected and SZG-HUB1450 operation continues. This is a non-latching fault. When the over-current condition stops, the eFuse continues normal operation and the power fault is removed automatically. A flickering red PWR LED typically means the eFuse is entering this state.
2. eFuse over-temperature protection engaged — If the eFuse remains in an over-current condition and cannot dissipate sufficient heat, it eventually enters an over-temperature fault. The eFuse opens and the power distribution system is disconnected. This is a latching fault. The SZG-HUB1450 must be reset by disconnecting the HOST and POWER inputs. A solid red PWR LED typically means the eFuse has entered this state.

Power to the +5V and +3.3V SYZYGY rails is enabled shortly after power-on. Voltage and timing of powering the VIO rails on the three SYZYGY power groups depends on the HUB1450_SMARTVIO_MODE device setting. See the SYZYGY Ports documentation for more information.

The table below can help determine the approximate power consumption for a specific SZG-HUB1450 application. Many of the values in the table are highly dependent on resource utilization, clock speeds, SYZYGY peripheral power consumption, and so on. Entries we have made are based on typical expected values presented in component datasheets or approximations based on AMD power estimator results. Shaded boxes represent unconnected rails to a particular component. Empty boxes represent data that you must provide based on power estimates. All values are shown in amps (A) unless otherwise specified.

1. Use the AMD Power Design Manager to estimate the FPGA power consumption in the first three rows of the table. The PDM tool allows you to input the parameters of your design (clock utilization, BRAM, DSP, I/O, etc.) and it provides an estimated current consumption for each voltage rail.
   • As an estimate for the USB host interface component, the table includes 0.020 A for FPGA VCCO 1.8 V.
   • If your design uses the DDR4 interface, include 0.071 A for FPGA VCCO 1.2 V
   • If your design uses SYZYGY, add the relevant I/O parameters for those interfaces according to the I/O count, I/O voltage, and signaling standard used by the peripherals. Add the VCCO current draw to the VIO1 and VIO2 columns.
2. If your design uses the DDR4 interface, include 0.179 A for DDR4 VDD/VDDQ and 0.384 A for DDR4 VTT termination (both in the 1.2 V column). This corresponds to the peak expected power consumption of the memory device.
3. If your SZG-HUB1450 includes an active fansink powered by the FAN connector, add 0.140 A in the 5V column.
4. If your application uses SYZYGY peripherals, include the peripheral current draw for each rail (3.3 V, 5 V, and VIO) for each port. The total 3.3 V and 5 V current draw for all three ports combined is limited to 2 A per rail.
5. Sum the currents in each column to get the total current per rail. These numbers must not exceed the available current per rail.
6. Multiply the rail voltage by the total rail current to get an estimated power consumption for each rail. To get the the total input power required by the SZG-HUB1450, sum the individual power per rail values and divide the total by 0.85 to approximate the losses of the switching power regulators. Note the SZG-HUB1450 is limited to a maximum power input of 45 W.

Below is an example power consumption estimate created using the procedure described above.

Design parameters and components:

• FPGA utilization:
  • Clock: 200 MHz, 60,000 fanout
  • Logic: 200 MHz, 10,000 logic LUTs, 5000 shift registers, 5000 distributed RAMs, 50,000 registers
  • BRAM 1: 18-bit, 200 MHz, 50 block RAMs, 50% toggle rate
  • BRAM 2: 36-bit, 200 MHz, 25 block RAMs, 50% toggle rate
  • DSP: 200 MHz, 200 slices, 12.5% toggle rate
• DDR4 interface
• Two SYZYGY peripherals attached to Ports A and B which use 8 LVDS pairs each (VIO1 = 1.8 V)
• A SYZYGY peripheral attached to Port C which uses 32 LVCMOS33 I/O (VIO2 = 3.3 V)
• Passive heatsink (no active fan)