The FrontPanel SDK and related design details are proprietary and confidential. This includes some of the details of the Bank 0 and Bank 65 configuration connections that FrontPanel uses to add advanced configuration features that are beyond the scope of a reference design.

For full details on the available configuration options see UG570 UltraScale Architecture Configuration User Guide from AMD. For a schematic based UltraScale+ configuration implementation see the AMD KCU116 Evaluation Kit.

See the Flash Memory page for details on the FPGA flash connection.

Bank 0 and Bank 65 VCCO are powered by 1.8V.

FrontPanel provides fast configuration over USB while also enabling gateware to be stored in onboard flash. The full design of this advanced configuration control is proprietary. More information on configuring from flash memory can be found on the Flash Memory page.

JTAG pins on Bank 0 are connected to on-board test points with minimal additional components. For details see the JTAG and SYSMON page.

SelectIO pull resistors and POR delay are configured for correct operation of the SZG-HUB1450 and other system components. Adjusting them is not recommended.

These signals are all controlled or monitored automatically by FrontPanel firmware for the specific
configuration modes required of the system. AMD FPGAs support a wide variety of configuration
options for various system requirements. Please see UG570 from AMD for further details.

FrontPanel assumes the default startup configuration behavior. Users should rely on the default startup settings defined by AMD.

Modifying any BITSTREAM.STARTUP.* setting is outside the supported use case and may lead to undefined behavior during configuration.