The signals that connect the on-board USB microcontroller to the FPGA comprise the FrontPanel Host Interface and are used for configuration downloads and data communication with the FPGA. This interface is implemented by Opal Kelly’s proprietary microcontroller firmware and proprietary FPGA HDL modules.

In the FPGA design, the interface is accessed through the proprietary okHost gateware module included with the FrontPanel SDK. The SDK also provides the required XDC constraints that map the Host Interface pins to the okHost module.

Opal Kelly does not provide schematics or documentation describing the internal operation of this interface. Everything required to deploy the Host Interface in your design is documented in the FrontPanel User’s Manual. The FrontPanel SDK also includes several example projects for each supported board, and the Pins tool may be used to generate a reference constraints file for your HDL design.

This section documents how the okHost module interfaces with the user’s gateware design.

The okHost module provides a clock to your design that is synchronous to the host interface. This clock must be used for all pipe interfaces unless clock synchronizers (e.g. asynchronous FIFOs) are used to cross a clock boundary to another system clock.

The okHost provides an internal active-high BOARD_READY signal. This signal is asserted high when all board specific configuration is completed by the firmware, which includes setting up device sensors and configuring adjustable bank voltage rails. The signal will remain asserted from then on, and is never de-asserted.