FrontPanel Classic gives your design a fixed set of named endpoints: WireIn and WireOut, TriggerIn and TriggerOut, PipeIn and PipeOut, the addressable Register Bridge, and Block-Throttled Pipes. Moving to a FrontPanel AXI board changes only the design interface. FrontPanel AXI okHost replaces those named endpoints with three standard AXI interfaces that it presents to your logic.

In FrontPanel Classic, your design is built from a fixed set of predefined endpoint types. Each type has a fixed behavior and its own reserved address range, you instantiate up to 32 of each, and the host addresses them by endpoint.

FrontPanel AXI removes those predefined types. okHost presents three standard AXI interfaces, and you lay out the register map on AXI-Lite, the memory map on AXI-Full, and the stream or streams on AXI-Stream. The host reaches them with generic AXI reads and writes to the addresses you assign.

Because the design interface is now standard AXI, the whole AXI ecosystem is open to you, from interconnects and CSR generators to DDR and MIG controllers and third-party AXI IP.

Each Classic endpoint has a standard AXI equivalent that you build yourself.

The Wire and Trigger rows all become AXI-Lite registers, which you build following the CSR Recipe. For the Pipe rows, choose AXI-Stream for streaming data or AXI-Full for memory-mapped access; see okHost Core.

The migration also changes your host software. The FrontPanel API swaps the Classic endpoint methods for generic AXI reads and writes on the per-interface classes okCFrontPanelAXILite, okCFrontPanelAXIFull, and okCFrontPanelAXIStream. The full signatures are in the FrontPanel API reference.

The staged calls collapse. A Classic WireIn set-then-update,

dev.SetWireInValue(0x00, ctrl);
dev.UpdateWireIns();Code language: C++ (cpp)

becomes a single AXI-Lite write:

axiLite.Write(CTRL_ADDR, ctrl);Code language: C++ (cpp)

The clearest way to see the whole conversion is our examples, which ship the Counters sample in both forms: the Classic Counters.v and its AXI rewrite counters_csr.v, a single AXI-Lite CSR block. Build your CSR the same way, by hand for a small map or with a generator for a larger one, under Building Your CSR.

Each Classic endpoint becomes one register pattern. The Counters sample implements all four.

The two trigger patterns are the ones without a plain-register analog, so they are worth seeing in the gateware. A TriggerIn register clears to 0 every cycle by default. When an AXI-Lite write to the register is accepted, the case assignment overrides that default for one cycle, so each written bit pulses for a single clock:

// counters_csr.v: TriggerIn is a write-only register that pulses for one cycle
always @(posedge aclk) begin
    trig_ctrl_reg <= 32'd0;                          // default: clear every cycle
    if (/* an AXI-Lite write is accepted */) begin
        case (s_axil_awaddr)
            CSR_ADDR_TRIG_CTRL: trig_ctrl_reg <= s_axil_wdata;  // the write overrides for one cycle
        endcase
    end
endCode language: Verilog (verilog)

A TriggerOut register is the mirror. It accumulates each event bit by default, and when an AXI-Lite read of the register is accepted, the case returns those bits and clears them, so a polled read reports whether the event happened since the last read:

// counters_csr.v: TriggerOut holds each event until the host reads it
always @(posedge aclk) begin
    trig_status_store <= trig_status_store | trig_status;   // default: each event bit sticks
    if (/* an AXI-Lite read is accepted */) begin
        case (s_axil_araddr)
            CSR_ADDR_TRIG_STATUS: begin
                s_axil_rdata      <= trig_status_store | trig_status;  // return the bits
                trig_status_store <= 32'd0;                            // the read clears them
            end
        endcase
    end
endCode language: Verilog (verilog)

The Pipe replacement, bulk data, takes two shapes in our PerfTest example. For memory-mapped access, an AXI-Full region maps the pattern space to 0x1000_0000 through 0x1FFF_FFFF. For streaming data, s_axis and m_axis carry the pattern to the stream checker and generator.

With the mapping and the recipe in hand, a migration follows a fixed sequence.

1. Pick an AXI board. Choose a FrontPanel AXI board and its bandwidth mode.
2. Inventory your Classic design. List every Wire, Trigger, Pipe, and Block-Throttled Pipe with its role, direction, and width.
3. Map each endpoint to AXI using the concept-mapping table.
4. Copy the matching register pattern for each endpoint from The CSR Recipe and the Counters sample.
5. Design the AXI side. Assemble the CSR block and your logic, and add an AXI interconnect if you have more than one Subordinate, under Interface Routing and AXI Libraries and IP.
6. Instantiate and build. Bring okHost in place of the Classic okHost and build the bitstream, under Integrating okHost and Getting Started.
7. Rework the host software to the FrontPanel API AXI calls.
8. Verify in simulation with the okHost BFM, under Simulation, then on hardware.

• okHost Core: the AXI contract okHost presents, with its interfaces, behaviors, and per-interface specifics.
• System Design: interface routing, building your CSR, and the integration spine.
• Getting Started: get, build, and load a design.
• Simulation: verify against okHost with the BFM before hardware.
• FrontPanel API: the host-software side of the migration.
• FrontPanel Classic HDL: the endpoint model you are coming from.