This technical reference covers both the FrontPanel Subsystem and LEDs Vivado IP cores. The IP Cores’ configuration parameters are used when generating the IP Cores’ output products. The IP Cores’ parameters are validated to ensure they conform to the requirements specified in tables 3.1, 3.2, and 3.3. The FrontPanel Subsystem IP supports both board families; the LEDs IP Core is supported on FrontPanel Classic boards only.

The FrontPanel Subsystem IP serves two board families, and each of its parameters applies to one or both of them. On FrontPanel Classic boards you configure Wire, Trigger, and Pipe endpoints. On FrontPanel-AXI boards the IP delivers the okHost gateware documented in the FrontPanel AXI HDL pages, and its parameters instead select the bandwidth mode and optional output ports. Every parameter’s applicability is marked in the Applies to column of Table 3.1: All, Classic (the FX3 board type), or AXI (the FX4 board type). The board’s type is set automatically from the BOARD parameter; see Table 3.3.

The parameters can be set through TCL using the following command structure:

set_property -dict [list CONFIG.<Param Name> {<value>} <Additional Param/value pairs>] [get_ips <IP Instance>]Code language: HTML, XML (xml)Code language: HTML, XML (xml)

For example, on a FrontPanel Classic board configuring a WireIn endpoint:

set_property -dict [list CONFIG.BOARD {XEM8320-AU25P} CONFIG.WI.COUNT {1} CONFIG.WI.ADDR_0 {0x08}] [get_ips frontpanel_example]Code language: CSS (css)Code language: CSS (css)

And on a FrontPanel-AXI board selecting a bandwidth mode:

set_property -dict [list CONFIG.BOARD {SZG-HUB1450-AU10P-10G} CONFIG.FX4.MODE {Mode 3 (10G Up/2.5G Down)}] [get_ips frontpanel_example]Code language: CSS (css)Code language: CSS (css)

Currently, the XEM8350 is the only device to support a secondary Host Interface. Devices supporting the secondary Host Interface provide additional parameters by prepending an “S” field onto their counterparts laid out in Table 3.1. These parameters have identical functionality and the same validation/conformity rules as their counterparts. For brevity, these parameters are removed from Table 3.1:

• S.<type>.COUNT
• S.<type>.ADDR_<31-0>
• S.RB.EN

Additionally, S.EN is used to enable the secondary host interface and is listed in Table 3.1.

The parameters are categorized into the Types defined below:

The Applies to column marks each parameter’s board applicability: All boards, Classic (FX3) boards only, AXI (FX4) boards only, or a specific list of boards.

Table 3.1 FrontPanel Subsystem IP Core Parameters

Notes:

1. The included address bins start at <type>.ADDR_0 through to the <type>.COUNT specified, i.e., a <type>.COUNT of 3 will generate endpoints for the addresses in bins <type>.ADDR_0 through <type>.ADDR_2.
2. PI & BTPI Endpoint types share the same address space. Their summed COUNTs cannot exceed 32, i.e. PI.COUNT + BTPI.COUNT ≤ 32.
3. PO & BTPO Endpoint types share the same address space. Their summed COUNTs cannot exceed 32, i.e. PO.COUNT + BTPO.COUNT ≤ 32.
4. Addresses must be in HEX format, i.e., 0x04.
5. No two Endpoint address bins can have the same address.
6. Only supported on boards with FPGA Flash.
7. Not intended outside of the GUI flow.
8. Internal Parameter is automatically configured appropriately based on the BOARD parameter.
9. The mode set available depends on the board. Boards that are not FrontPanel-AXI are locked to Mode 1 (10G Up/40M Down) and the control is disabled. The bandwidth mode is fixed at build time.
10. The SYSMON I2C pins share a variable-VIO I/O bank with a SYZYGY port; the selected voltage must match that bank. Only configurable on boards whose SYSMON pins are on a variable bank.

Table 3.2 LEDs IP Core Parameters

Notes:

1. Used for boards whose LEDs are connected to a variable bank voltage controlled by VIO.

For the selected BOARD parameter, the IP Core will check the project’s currently configured FPGA part. If it does not match the associated FPGA part displayed in the table below, referred to as the “Enforced FPGA Part,” the IP Core will restrict generation until the issue is resolved. The Type column indicates the board family: FX3 (FrontPanel Classic) or FX4 (FrontPanel-AXI).

Table 3.3 Allowed Entries for BOARD Parameter