This page covers using the FrontPanel Subsystem IP Core in Vivado’s IPI Block Designer for AXI and Classic boards.

The FrontPanel Subsystem IP Core exposes AXI interfaces, documented in okHost Core. The screenshot below shows how the IP appears in a block design.

For working with AXI interfaces in IPI, refer to AMD’s documentation:

• Vivado Design Suite: AXI Reference Guide (UG1037) — AXI4-Full, AXI4-Lite, and AXI4-Stream protocol variants
• Designing IP Subsystems Using IP Integrator (UG994) — interface-level connections and Designer Assistance in IPI
• AXI4-Stream Infrastructure Product Guide (PG085) — AXI4-Stream interconnect and streaming interface connections

For designing a system around okHost’s AXI interfaces (routing to multiple Subordinates with an interconnect, crossing clock domains, and building a CSR block), see System Design in the FrontPanel AXI HDL documentation.

This tutorial walks through connecting your RTL to okHost’s FrontPanel endpoint interfaces in IPI, using the generated interface template with PipeTest as a complete working example.

This tutorial produces the block diagram below. The _DESCRIPTION tags come from the generated RTL port interface template. Substitute these tags with the utility the endpoint is providing to the RTL module, i.e. pipein80_video_feed.

1. Basics
   1. Add IP Cores’ Distribution to Vivado.
   2. Create an IP Core Compatible Vivado Project.
2. Instantiate IP Core in IP Integrator (IPI) Block Design
   1. Click Create Block Design.
   2. If using an Opal Kelly Board file, see Add FrontPanel Board Component in IPI and skip to step 3. Configuring & Generating the IP Core. Otherwise, right-click in the Block Designer and select Add IP.
   3. Search for the FrontPanel Subsystem IP Core and double-click it.
   4. Right-click on host_interface and select Make External. (See Port Requirements Technical Reference for more information.)
3. Configuring & Generating the IP Core
   1. Double-click on the FrontPanel Subsystem IP Block to open it up for configuration.
   2. On the Endpoints page:
      1. Enter a count of “1” for each of the Endpoint types. Leave the addresses at their defaults.
      2. Enable the Register Bridge Endpoint.
   3. Click OK.
   4. Click Generate Block Design.
4. Adding an RTL module & Using the Interface Template
   1. Add an empty RTL module to the Vivado Project.
   2. Find _bd_interface_template.vh located in the Synthesis folder in the IP Sources panel.
   3. Copy the contents of this template into the port definitions of the empty RTL module. Remove the trailing comma from the last port definition.
   4. Right-click on the RTL module in Design Sources and select Add Module To Block Design.
5. Establish Interface Connections in IPI
   1. Make interface-to-interface connections from the IP Core to the RTL module in the IPI Block Designer.
6. Running the PipeTest IPI Block Designer Example Design
   1. For a complete IPI Block Designer example, open the PipeTest Block Designer Example Design. See the Example Designs tutorial for instructions on opening this example design.