The okHost Bus Functional Model (BFM) stands in for okHost and the USB transport, so you can exercise a FrontPanel AXI okHost design in simulation. Your testbench calls host API operations, and the BFM drives them onto your design’s AXI interfaces.

The BFM is footprint-compatible with the synthesis okHost, sharing the same module name and port list, so swapping it in changes only the file, not your instantiation, connections, or signal names. It is also a behavioral model rather than the synthesis RTL. The transport pins (okUHU, okUH, okHU) play no role in simulation and are width-1 stubs.

The BFM comes in two flavors, Verilog (Vivado XSim) and cocotb (Python); they run the same behaviors and differ only in the testbench language and toolchain.

Both the simulation and synthesis builds of okHost honor the same behavioral contract, but they are different implementations of it. The synthesis build is RTL for the FPGA; the simulation build is a behavioral model for the simulator. The documented behaviors are identical. The precise cycle timing is not, because the two are coded in different styles, so treat the match as behavioral, not cycle-accurate.

The BFM also leaves out the host transport entirely, so no transport-specific behavior appears. If your transport is USB, for example, there are no idle gaps, and USB endpoint arbitration on a shared USB host controller is not represented.

The Verilog BFM (okHost.vp) and the cocotb BFM (frontpanel.py) reproduce okHost’s documented behaviors identically. The BFM runs one operation at a time; a call made while another is in progress returns UnsupportedFeature. Both BFMs return the same numeric error codes as the hardware. The full catalog is on the SDK Error Codes page; what the gateware-related codes mean and how to recover are on Error Handling.

The BFM can exercise your design under sparse, irregular handshakes by scattering idle cycles into a channel. Stall injection is configured per channel: AXI-Full write (WVALID) and read (RREADY), and AXI-Stream write (TVALID) and read (TREADY). AXI-Lite has no stall injection. Each channel takes either a percent density, 0 to 100, which the BFM expands into a reproducible pseudo-random pattern, or an explicit looping pattern. The default is no stall.

For example, a percent of 25 stalls the channel on about one cycle in four, with the stalled cycles placed by a reproducible pseudo-random sequence, so a run repeats. A pattern sets an exact repeating cadence instead, its bits marking which cycles run and which stall. The bits are consumed least-significant bit first, so 1110 stalls one cycle and then runs three, over and over.

PerfTest is the shared FrontPanel-AXI example design. Its DUT and architecture, the data patterns it exercises, and how to build and run it on hardware live on the PerfTest example page. In simulation, the okHost BFM drives that same DUT across all three interfaces, in each of the bandwidth modes from the USB Transport table.

Both flavors verify the same behaviors:

• reads and writes across every data pattern,
• AXI-Full burst splitting at the 4 KB boundary,
• gateware timeouts, with the partial byte and transaction counts checked,
• backpressure through stall injection,
• rejection of unaligned transfers,
• injected AXI response errors (SLVERR and DECERR).

The Verilog and cocotb children each show how to run this suite and the pass count to expect.

• okHost Core: the hardware AXI contract the BFM reproduces.
• USB Transport: the bandwidth-mode table (data widths and clock).
• System Design: integrating okHost and diagnosing with the counts.
• Getting Started: building the PerfTest example on the SDK path.
• Verilog (Vivado XSim): the Verilog simulation child.
• cocotb (Python): the cocotb simulation child.