Opal Kelly Pins is an interactive online reference for the expansion connectors on all Opal Kelly FPGA integration modules. It provides additional information on pin capabilities, pin characteristics, and PCB routing.
Pins can also generate constraint files (XDC) and help you map your HDL net names to FPGA pin locations automatically.
The Pins reference for the XEM7001 may be found at the link to the right.
Three 0.1”-spaced expansion connectors (JP1, JP2, JP3) are available to connect the module to your devices. These connectors provide 3.3V power, ground, PLL outputs, and 90 FPGA pins for general I/O. Of the 90 FPGA pins, two are SRCC (single region clock inputs) one is a single ended MRCC (multi-region clock input) and one is a differential MRCC. All expansion connectors are on a 0.1” grid so that the entire module can piggy-back onto a standard 0.1” PCB protoboard.
JP1 is a 20-pin dual-row 100-mil header, four pins of which are dedicated to power supply. The other 16 pins connect directly to the Artix 7 on bank 35. A multi-region clock-capable input (MRCC) is available as a differential pair on pins 17 (+) and 18 (-). Pin 17 may be used as a single-ended MRCC, but single-ended usage is not available on pin 18. All 16 FPGA pins may be used as general-purpose input/output.
JP2 is a 50-pin dual-row 100-mil header providing access to FPGA banks 34 and 35. Several pins of this header are dedicated to power supply (+3.3VDD and DGND). Pin 4 of this header is connected to a single-region clock input (SRCC) on bank 14.
Pin 3 on this header is SYS_CLK5 and is directly connected to LCLK5 (pin 14) on the Cypress CY22150 PLL. Using FrontPanel’s PLL Configuration Dialog, you can configure the clock signal present on this pin.
JP3 is a 50-pin dual-row 100-mil header providing access to FPGA bank 15. Several pins of this header are dedicated to power supply (+3.3VDD and DGND). Pin 47 of this header is connected to a multi-region clock input (MRCC) on the FPGA and can therefore be used as an input to the internal clock network.
Pin 48 on this header is SYS_CLK4 and is directly connected to LCLK4 (pin 12) on the Cypress CY22150 PLL. Using FrontPanel’s PLL Configuration Dialog, you can configure the clock signal present on this pin.
JP4 – JTAG Header
JP4 is the 14-pin 2-mm JTAG connector on-board and is connected only to the FPGA. The connector pinout is compatible with the Xilinx JTAG cable for JTAG configuration and ChipScope. The JP4 pins are connected as shown below:
|1, 3, 5, 7, 9, 11, 13||DGND|