The PLL contains six output pins, one of which is left unconnected. The other five are labelled SYS_CLK1 through SYS_CLK5. SYS_CLK4 connects to JP3 and SYS_CLK5 connects to JP2. The other three pins are connected directly to the FPGA. The table below illustrates the PLL connections.
|PLL PIN||CLOCK NAME||CONNECTION|
|LCLK1||SYS_CLK1||FPGA – N14 (Bank 14, MRCC)|
|LCLK2||SYS_CLK2||FPGA – F4 (Bank 35, SRCC)|
|LCLK3||SYS_CLK3||FPGA – F5 (Bank 35, MRCC)|
|LCLK4||SYS_CLK4||JP3 – Pin 48|
|CLK5||SYS_CLK5||JP2 – Pin 3|