On-Board PLL

PLL Connections

The PLL contains six output pins, one of which is left unconnected.  The other five are labelled SYS_CLK1 through SYS_CLK5.  SYS_CLK4 connects to JP3 and SYS_CLK5 connects to JP2.  The other three pins are connected directly to the FPGA.  The table below illustrates the PLL connections.

PLL PINCLOCK NAMECONNECTION
LCLK1SYS_CLK1FPGA – N14 (Bank 14, MRCC)
LCLK2SYS_CLK2FPGA – F4 (Bank 35, SRCC)
LCLK3SYS_CLK3FPGA – F5 (Bank 35, MRCC)
LCLK4SYS_CLK4JP3 – Pin 48
CLK5SYS_CLK5JP2 – Pin 3
CLK6Not Connected