The XEM6310 was designed to be as compatible as possible with our XEM6010 in order to facilitate customer design migration with minimal changes. The physical dimensions and connector footprints are identical. The differences between these two products are highlighted below.
FPGA Boot Configuration
The XEM6010 has a small flash memory attached to the FPGA that could be used for FPGA boot configuration. The XEM6310 has a larger flash memory attached to the USB microcontroller that allows the microcontroller to boot from one of multiple boot images stored. The XEM6310 also has a separate flash memory attached to the FPGA that may not be used for boot configuration.
Clock PLL → Clock Oscillator
The XEM6010 has a Cypress CY22393 multi-output PLL that provided clock signals to the FPGA and expansion connectors. The XEM6310 has a fixed-output 100 MHz clock oscillator that provides this clock signal to the FPGA. The FPGA has on-board DCMs and PLLs which may be used to produce a wide range of clock frequencies. The expansion connector signals that were routed to the CY22393 on the XEM6010 are routed to the FPGA on the XEM6310.
Expansion Connector Differences
There are some minor differences between the XEM6010 and XEM6310 expansion connector pinouts. The location and type of connector is unchanged.
• JP3 on the XEM6010 is the same connector and location as JP1 on the XEM6310. This connector reference designator has changed.
• The XEM6310 has two connections on the expansion bus to support the Vbatt functionality of the LX150 Spartan-6 FPGA to store encryption keys. This functionality is not available in the LX45.
• The XEM6010 provided the USB microcontroller (FX2) I2C signals to the expansion connector. The XEM6310 routes these two signals to the FPGA. If this support is required, an I2C controller will need to be implemented in FPGA fabric.
The following table summarizes the expansion connector differences:
|JP2-3 is a no-connect||JP2-3 is FPGA Vbatt|
|JP2-12 is a no-connect||JP2-12 is FPGA Rfuse|
|JP2-11 is PLL SYS_CLK4||JP2-11 is FPGA U12 (Bank 2, 1.8v)|
|JP3-8 is PLL SYS_CLK5||JP1-8 is FPGA T14 (Bank 2, 1.8v)|
|JP3-10 is the FX2 SCL signal||JP1-10 is FPGA Y9 (Bank 2, 1.8v)|
|JP3-12 is the FX2 SDA signal||JP1-12 is FPGA AB9 (Bank 2, 1.8v)|