The Spartan-6 FPGA supports design security using AES decryption logic and provides two methods for encryption key memory storage. The first is a volatile memory storage supported by an external battery backup supply voltage (Vbatt). The second is a one-time programmable eFUSE. The XEM6310 design supports both types of key storage with user-modification required.
For quantity purchases of 50 or more units, please contact Opal Kelly (firstname.lastname@example.org) to discuss factory installation of these components.
Volatile Encryption Key Storage (Vbatt)
A small lithium rechargeable battery and three support components can be installed to provide Vbatt to the FPGA when the XEM is unpowered. This will preserve the contents of the FPGA’s volatile key storage so long as Vbatt remains over the threshold specified in the Spartan-6 documentation. Please see the Xilinx Spartan-6 FPGA Configuration User Guide (UG380) for more details. Alternatively, Vbatt may be provided through JP2-3. In this case, BT1 should not be installed.
The applicable schematic section and components required to support this functionality are shown below.
|BT1||Seiko Instruments||MS412FE-FL26E||3V, 1mAh lithium battery|
|D10||Micro Commercial||BAS40-04-TP||Schottky Diode, SOT23|
|C150||Generic||0.1 μF, SM-0402||Decoupling|
|R43, R44||Generic||4.7 kΩ, 5%, SM-0402|
|R41||Generic||0 Ω, SM-0402||Connects Vbatt to JP2-3|
Non-Volatile Encryption Key Storage (eFUSE)
Non-volatile storage of the encryption key is also possible by programming the Spartan-6 eFUSE via JTAG. Please see the Xilinx Spartan-6 FPGA Configuration User Guide (UG380) for more details.
To program the eFUSE, you must first install the components listed in the table below. You must also provide an external resistor (Rfuse) between JP2-12 and GND. The value of this resistor is specified in the Xilinx Spartan-6 Datasheet (DS162) between 1129 Ω and 1151 Ω.
|C149||Generic||0.1 μF, SM-0402||Decoupling|
|R7||Generic||0 Ω, SM-0402||Connects FPGA Vfs to +3.3v|
|R42||Generic||0 Ω, SM-0402||Connects FPGA Rfuse to JP2-12|