DDR2 SDRAM

The Micron DDR2 SDRAM is connected exclusively to the 1.8-V I/O on Bank 3 of the FPGA.  The tables below list these connections.

DDR2 PINFPGA PIN
CKH4
CK#H3
CKED2
CS#C3
RAS#K5
CAS#K4
WE#F2
LDQSL3
LDQS#L1
UDQST2
UDQS#T1
LDML4
UDMM3
ODTJ6
DDR2 PINFPGA PIN
A0H2
A1H1
A2H5
A3K6
A4F3
A5K3
A6J4
A7H6
A8E3
A9E1
A10G4
A11C1
A12D1
BA0G3
BA1G1
BA2F1
DDR2 PINFPGA PIN
D0N3
D1N1
D2M2
D3M1
D4J3
D5J1
D6K2
D7K1
D8P2
D9P1
D10R3
D11R1
D12U3
D13U1
D14V2
D15V1

Clock Configuration (Source Synchronous)

The DDR2 clocking is designed to be source-synchronous from the FPGA.  This means that the FPGA sends the clock signal directly to the SDRAM along with control and data signals, allowing very good synchronization between clock and data.

Memory Controller Blocks

Spartan-6 has integrated memory control blocks to communicate with the external DDR2 memory on the XEM6310.  This is instantiated using the Xilinx Core Generator (memory interface generator, or MIG) to create a suitable memory controller for your design.  You should read and become familiar with the DDR2 SDRAM datasheet as well as MIG and the core datasheet.  Although MIG can save a tremendous amount of development time, understanding all this information is critical to building a working DDR2 memory interface.

The XEM6310 provides 1.2 V as Vccint.  According to the memory controller block documentation, the Spartan-6, -2 speed grade can operate memory to 312.5 MHz with this internal voltage.

MIG Settings

The following are the settings used to generate the MIG core for our RAMTester sample using Xilinx Core Generator.  These settings were used with ISE 12.2 and MIG 2.3.  Note that settings may be slightly different for different versions of ISE or MIG.

Frequency312.5 MHz 
Memory TypeComponent 
Memory PartMT47H64M16XX-3 (1Gb, x16) 
Data Width16 
Enable DQS EnableCHECKED 
High-temp self-refreshDISABLED 
Output drive strengthReducedstrength 
RTT(nominal)50 ohms[default]
DCI for DQ/DQSCHECKED 
DCI for address/controlCHECKED 
ZIO pinY2 
RZQ pinK7 
Calibrated Input SelectionYes 
Class for address/controlClass II 
Debug signalsYour option 
System clockDifferential