Opal Kelly Pins is an interactive online reference for the expansion connectors on all Opal Kelly FPGA integration modules. It provides additional information on pin capabilities, pin characteristics, and PCB routing.

Pins can also generate constraint files (XDC) and help you map your HDL net names to FPGA pin locations automatically.

The Pins reference for the XEM7310 may be found at the link to the right. 

Two high-density, 80-pin expansion connectors are available on the bottom-side of the XEM7310 PCB. These expansion connectors provide user access to several power rails on the XEM7310, the JTAG interface on the FPGA, and 126 I/O pins on the FPGA, including several MRCC clock inputs.

The connectors on the XEM7310 are Samtec part number: BSE-040-01-F-D-A. The table below lists the appropriate Samtec mating connectors along with the total mated height.

MC1 is an 80-pin high-density connector providing access to FPGA Banks 34 and 13. Several pins of this connector are wired to clock inputs on the FPGA, see the table below and the Xilinx Artix-7 documentation for more details.

Pin mappings for MC1 are listed on the pins page linked above. For each pin, the corresponding board connection is listed. For pins connected to the FPGA, the corresponding FPGA pin number is also shown. Finally, for pins routed to differential pair I/Os on the FPGA, the FPGA signal names and routed track lengths have been provided to help you equalize lengths on differential pairs.

Note that MC1 pins 64 and 66-76 are attached to FPGA Bank 13 which is powered as a 3.3 V bank. This may not be changed.

MC2 is an 80-pin high-density connector providing access to FPGA Bank 35 and 13. Several pins of this connector are wired to clock inputs on the FPGA, see the table below and the Xilinx Artix-7 documentation for more details.

Pin mappings for MC2 are listed on the pins page linked above. For each pin, the corresponding board connection is listed. For pins connected to the FPGA, the corresponding FPGA pin number is also shown. Finally, for pins routed to differential pair I/Os on the FPGA, the FPGA signal names and routed track lengths have been provided to help you equalize lengths on differential pairs.

Note that MC2 pins 64 and 66-76 are attached to FPGA Bank 13 which is powered as a 3.3 V bank. This may not be changed.

Available clock pins are illustrated in the table below. All pins listed are multi-region clock pins.

The table below describes the power supply configuration of the FPGA banks on the XEM7310. Note that the bank voltages for banks 13, 14, 15, and 16 may not be changed. VCCO_MC1 and VCCO_MC2 are connected to 3.3v by factory default.

The Artix-7 FPGA allows users to set I/O bank voltages in order to support several different I/O signal standards. This functionality is supported by the XEM7310 by allowing the user to connect independent supplies to the FPGA VCCO pins on two of the FPGA banks.

By default, ferrite beads (P/N Steward HZ0402B102R-10) have been installed that attach each VCCO bank to the +3.3VDD supply. If you intend to supply power to a particular I/O bank, you MUST remove the appropriate ferrite beads. Power can then be supplied through the expansion connectors.

The table below lists details for user-supplied I/O bank voltages

For pin connection details see the Pins page.

For information on FPGA power supply startup sequencing when using external I/O voltages, see Powering the XEM7310.

The Artix-7 family of devices has the following recommended power supply startup sequence:

1. VCCINT/VCCBRAM
2. VCCAUX
3. VCCO

This sequence achieves minimum current draw and ensures I/O are tristated at power-on. For more information see the “Power-On/Off Power Supply Sequencing” section in the Artix-7 FPGA Data Sheet (DS181).

To meet this sequencing recommendation when applying external VCCO power supplies, the external system should monitor the XEM7310 +1.8VDD supply on mezzanine connector MC1, pin 7. This on-board voltage rail powers the FPGA VCCAUX pins directly. After the +1.8VDD rail is within regulation (within ±10%, for example), the external system may apply VCCO to the module.

The Xilinx Artix-7 XADC feature is routed through two 1kΩ resistors to the MC1 connector. There is a 0.01 µF capacitor installed across the two FPGA pins for decoupling.

The XEM7310 PCB layout and routing has been designed with several applications in mind, including applications requiring the use of differential (LVDS) pairs. Please refer to the Xilinx Artix-7 datasheet for details on using differential I/O standards with the Artix-7 FPGA.

In order to use differential I/O standards with internal termination on the Artix-7, you must set the VCCO voltages for the appropriate banks to 2.5V according to the Xilinx Artix-7 datasheet.

Because the bank 13 VCCO is fixed at 3.3V, it’s use of LVDS is limited. For more information on using LVDS with bank 13 see the LVDS and LVDS_25 (Low Voltage Differential Signaling) section of 7 Series FPGAs SelectIO Resources User Guide (UG471).

The characteristic impedance of all routes from the FPGA to the expansion connector is approximately 50Ω.

In many cases, it is desirable that the route lengths of a differential pair be matched within some specification. Care has been taken to route differential pairs on the FPGA to adjacent pins on the expansion connectors whenever possible. We have also included the lengths of the board routes for these connections to help you equalize lengths in your final application. Due to space constraints, some pairs are better matched than others.

The Xilinx Artix-7 supports both internal and externally-applied input voltage thresholds for some input signal standards. The XEM7310 supports these Vref applications for banks 13, 34, and 35. Please see the Xilinx Artix 7 documentation for more details.

For Bank 34, the two Vref pins are routed to expansion connector MC1 on pins 22 and 52. Note that both pins must be connected to the same voltage for proper application of input thresholds. Please see the Xilinx Artix-7 documentation for more details.

For Bank 35, the two Vref pins are routed to expansion connector MC2 on pins 21 and 57. Note that both pins must be connected to the same voltage for proper application of input thresholds. Please see the Xilinx Artix-7 documentation for more details.

For Bank 13, the single Vref pin is routed to expansion connector MC2 on pin 74. Please see the Xilinx Artix-7 documentation for more details.

MC2 has an optional connection to the FPGAs VCCBATT pin E12. By default this MC2 pin is not connected, and the FPGA VCCBATT pin E12 is connected to GND via the 0 Ohm resistor R89. For external access to VCCBATT remove R89 and place a 0 Ohm resistor on R51.

For more information on VCCBATT see Encryption Key Storage.

Xilinx Artix-7 FPGAs support a weak pull-up state on all I/O pins from power on until first configuration. This behavior is controlled by the PUDC_B pin. By default the XEM7310 holds the PUDC_B pin high with a 1kΩ resistor at R26, disabling the weak pull-up on all I/O pins at power on. This behavior can be changed by inserting a 0Ω resistor at R28 and removing the 1kΩ resistor at R26, forcing the PUDC_B pin to ground.