A fixed-frequency, 200 MHz, low-jitter oscillator is included on-board and outputs LVDS to the FPGA on bank 13. The Artix-7 FPGA can produce a wide range of clock frequencies using the on-chip DCM and PLL capabilities.
|200 MHZ PIN||FPGA PIN|
Internal LVDS input termination must be disabled on these pins to function properly (
DIFF_TERM=FALSE). External termination is provided on the board. This is necessary when using the LVDS clock input on bank 13 as this bank is fixed at 3.3V VCCIO. Please see Xilinx’s UG471 for more details.