The XEM7310 was designed to be as compatible as possible with our XEM6310 in order to facilitate customer design migration with minimal changes. The physical dimensions and expansion connector locations are identical. The differences between these two products are highlighted below.
Note that this migration guide does not discuss differences between the Spartan-6 and Artix-7 FPGA architectures, features, capabilities, or limitations. Please consult the Xilinx documentation for more information.
128 MiB DDR2 SDRAM → 1 GiB DDR3 SDRAM
The XEM7310 has larger, faster, and more modern memory and has a 32-bit data bus as opposed to the 16-bit data base on the XEM6310. The Xilinx memory controller on Artix-7 consumes fabric resources unlike the hard memory controller on the Spartan-6.
100 MHz Oscillator → 200 MHz Oscillator
The system oscillator has been changed to a 200 MHz oscillator.
Expansion Connector Differences
- The XEM6310 routed the USB I2C connections to the expansion connector enabling the use of the I2C API functions. On the XEM7310, these have been removed. In their place, the XADC pins from the FPGA have been routed. This provides expansion access to the FPGA’s internal analog-to-digital converter.
- The Rfuse signal on the XEM6310 expansion connector JP2-12 has been removed. An FPGA I/O pin has been routed to this pin on the XEM7310.
- FPGA differential pair connections have been preserved. In other words, a pair that existed on two expansion connectors on the XEM6310 are also connected to an I/O pair on the XEM7310. Route lengths, however, have changed. Please review the Pins table if this is a concern.
- I/O Voltage adjustments are no longer possible for all expansion connector pins. Pins on bank 13 of the XEM7310 are fixed at 3.3V. More information can be found on the Expansion Connectors page.
- The VCCIO requirements for various I/O standards (including LVDS) have changed from the Spartan 6 to the Artix 7, please refer to the Xilinx documentation for more details.
|JP1-4 and 6 are +1.2VDD||MC1-4 and 6 are +1.0VDD|
|JP1-10 is FPGA fabric I/O||MC1-10 is XADC_VN|
|JP1-12 is FPGA fabric I/O||MC1-12 is XADC_VP|
|JP2-10 is FPGA VREF||MC2-10 is FPGA fabric I/O|
|JP2-11 is PLL CLK4||MC2-11 is FPGA fabric I/O|
|JP2-12 is FPGA Rfuse||MC2-12 is FPGA fabric I/O|