DDR3 Memory
The DDR3 SDRAM is connected to the 1.5-V I/O on Bank 7A and 8A of the FPGA. The tables below list these connections.
The following resources are available to help provide guidance for designs that involve this memory:
- The RAMTester sample reads and writes this memory via FrontPanel pipe endpoints.
- The Camera Reference Design provides a memory interface for frame buffering.
- The ZEM5305 Pins Reference can generate a constraints file (click on Export) with complete pin mapping and I/O constraints for use in your design.
Connection Tables
| DDR3 PIN | FPGA PIN |
|---|---|
| RESET | B22 |
| CK | J9 |
| CK# | J8 |
| CKE | B15 |
| CS# | H8 |
| RAS# | A9 |
| CAS# | A10 |
| WE# | E6 |
| DQS0 | H9 |
| DQS0# | G8 |
| DQS1 | G12 |
| DQS1# | H12 |
| DM0 | A15 |
| DM1 | C19 |
| ODT | A13 |
| DDR3 PIN | FPGA PIN |
|---|---|
| A0 | C11 |
| A1 | B11 |
| A2 | A8 |
| A3 | A7 |
| A4 | D11 |
| A5 | E11 |
| A6 | F8 |
| A7 | E7 |
| A8 | D9 |
| A9 | D8 |
| A10 | B6 |
| A11 | B5 |
| A12 | C8 |
| A13 | B8 |
| A14 | H6 |
| BA0 | C6 |
| BA1 | C10 |
| BA2 | C9 |
| DDR3 PIN | FPGA PIN |
|---|---|
| D0 | F12 |
| D1 | E12 |
| D2 | B12 |
| D3 | B13 |
| D4 | C13 |
| D5 | D13 |
| D6 | C14 |
| D7 | A14 |
| D8 | E14 |
| D9 | F15 |
| D10 | B18 |
| D11 | A17 |
| D12 | C15 |
| D13 | C16 |
| D14 | B16 |
| D15 | C18 |
DDR3 SDRAM Controller Settings
Cyclone V devices support external, high-performance memory through the use of the DDR3 SDRAM Controller with UniPHY provided by Altera. This provides a custom memory controller using the hard memory controller IP present on the Cyclone V devices. These parameters have been used successfully within Opal Kelly but your design needs may require deviations.
Parameters in Bold are those that need to be changed from the default.
All settings are based on Quartus II 15.0.2.
Screenshots of this process are available in the DDR3 Memory Walkthrough.
PHY Settings
| SECTION | PARAMETER | ZEM5305 |
|---|---|---|
| Enable Hard External Memory Interface | Enabled | |
| General Settings | Speed Grade | 8 |
| Clocks | Memory Clock Frequency | 333.3333 MHz |
| PLL Reference Clock Frequency | 100.0 MHz | |
| Rate on Avalon-MM interface | Full | |
| Enable AFI Half Rate Clock | Disabled | |
| Advanced PHY Settings | Supply Voltage | 1.5V DDR3 |
| PLL Sharing Mode | No Sharing | |
| DLL Sharing Mode | No Sharing | |
| OCT Sharing Mode | No Sharing |
Memory Parameters
Select the MICRON MT41K256M16HA-125 memory device preset and click “Apply”. This applies all memory parameters correctly with the following exceptions:
| SECTION | PARAMETER | ZEM5305 |
|---|---|---|
| Total Interface Width | 16 | |
| Memory Initialization Options | Output Drive Strength Setting | RZQ/6 |
| ODT Rtt Nominal Value | RZQ/6 | |
| Auto Selfrefresh Method | Automatic |
Memory Timing
These parameters are set after applying the preset for the Micron memory device above.
Board Settings
The default settings in this tab should be appropriate for the ZEM5305.
Controller Settings
| SECTION | PARAMETER | ZEM5305 |
|---|---|---|
| Avalon Interface | Generate power-of-2 data bus widths for Qsys or SOPC Builder | Disabled |
| Generate SOPC Builder Compatible Resets | Disabled | |
| Maximum Avalon-MM Burst Length | 128 | |
| Enable Avalon-MM Byte-enable Signal | Enabled | |
| Low Power Mode | All Options | Disabled |
| Efficiency | Enable User Auto-Refresh Controls | Disabled |
| Enable Auto-Precharge Control | Disabled | |
| Local-to-Memory Address Mapping | CHIP-ROW-BANK-COL | |
| Enable Reordering | Enabled | |
| Starvation Limit for Each Command | 10 commands | |
| Configuration, Status and Error Handling | All Options | Disabled |
| Multiple Port Front End | Export Bonding Interface | Disabled |
| Expand Avalon-MM Data for ECC | Disabled | |
| Number of Ports | 1 | |
| Port 0 | Type | Bidirectional |
| Width | 128 | |
| Priority | 1 | |
| Weight | 0 |
Diagnostics
| SECTION | PARAMETER | ZEM5305 |
|---|---|---|
| Simulation Options | Auto-calibration mode | Skip calibration |
| Skip Memory Initialization Delays | Enabled | |
| Enable Verbose Memory Model Output | Enabled | |
| Enable Support for Nios II ModelSim Flow in Eclipse | Disabled | |
| Debugging Options | All Options | Default |
| Efficiency Monitor and Protocol Checker Settings | All Options | Default |
DDR3 SDRAM Pin Assignments
After generating the DDR3 controller using the settings above, a set of pin assignments will be created for the memory interface. To apply these settings to a design you must first synthesize the design. Then, from the TCL Scripts tool found in the Quartus Tools menu select the ddr3_interface_p0_pin_assignments.tcl script and select Run. This should apply all required constraints to the design.