Hardware Design Guide

This reference is provided to help guide you through the design process of a mating peripheral to the ZEM5305. It is not intended to be a comprehensive instruction manual. While we put forth great effort to reduce the effort required to build an FPGA-enabled platform, there are hundreds of pages of product documentation from Intel that should be considered. Use this guide as a roadmap and starting point for your design effort.

Useful References

Electrical Design Guide

Input Power Supply Connection

Input power to the ZEM5305 must be applied through the two mezzanine headers. For a list of required supply voltages and pin locations on the headers, see Powering the ZEM5305. For a full list of mezzanine header pin assignments, see the ZEM5305 Pins Reference.

Total Power Budget

The total operating power budget is an important system consideration. The power budget for the ZEM5305 is highly dependent on the FPGA’s operating parameters and this can only be determined in the context of an actual target design.

See the Powering the ZEM5305 page for suggested power supply guidelines and expected operating currents.

FPGA I/O Bank Selection and I/O Standard

Details on the available standards can be found in the following Intel documentation:

  • Cyclone V Device Datasheet (CV-51002)
  • Cyclone V Device Handbook Volume 1: Device Interfaces and Integration (CV-5V2)

FPGA I/O Bank Selection and Voltage

The ZEM5305 VCCIO supplies must be provided externally over the two mezzanine headers. More information can be found on the Powering the ZEM5305 page. See the ZEM5305 Pins Reference for details about FPGA bank power assignments.

Mechanical Design Guide

Mezzanine Connector Placement

Refer to the ZEM5305 mating board diagram for placement locations of the mezzanine connectors (Samtec BTE series) and mounting holes. This diagram can be found on the Specifications page of the ZEM5305 documentation.

Confirm the Connector Footprint

For recommended PCB layout of the Samtec BTE connector, refer to the BTE footprint drawing on the Samtec BTE product page.

Confirm Mounting Hole Locations

Refer to the ZEM5305 Specifications for a comprehensive mechanical drawing. Also refer to the BRK5305 as a reference platform. The BRK5305 design files can be found in the Downloads section of the Pins website.

Confirm Other Mechanical Placements

Refer to the ZEM5305 mechanical drawing for locations of the USB jacks and the DC power jack. This drawing is available on the Specifications page of the ZEM5305 documentation.

Thermal Dissipation Requirements

Thermal dissipation for the ZEM5305 is highly dependent on the FPGA’s operating parameters and this can only be determined in the context of an actual target design. The type of FPGA cooling solution required for your design should be determined through thermal analysis and simulation as required.

Determine the Mated Board Stacking Height

The Samtec BSE-series connectors on the ZEM5305 mate with BTE-series connectors on the carrier board. The BTE series is available in several stacking height options from 5 to 30 mm. The stack height is determined by the “lead style” of the BTE connector.

Note that increased stack height can lead to decreased high-speed channel performance. Information on 3-dB insertion loss point is available on the Samtec website.