DDR3 Memory
The Micron DDR3 SDRAM is connected exclusively to the 1.5-v I/O on Banks 15 and 16 of the FPGA. The tables below list these connections.
The following resources are available to help provide guidance for designs that involve this memory:
- How-To Apply DDR MIG Settings and Vivado Board File to generate Xilinx’s MIG IP Core.
- The RAMTester sample reads and writes this memory via FrontPanel pipe endpoints.
- The Camera Reference Design provides a memory interface for frame buffering.
- The XEM7320 Pins Reference can generate a constraints file (click on Export) with complete pin mapping and I/O constraints for use in your design.
Connection Tables
| DDR3 PIN | FPGA PIN |
|---|---|
| RESET | F21 |
| CKp | J14 |
| CKn | H14 |
| CKE | G18 |
| RAS | J16 |
| CAS | H17 |
| WE | J20 |
| DQS0p | N22 |
| DQS0n | M22 |
| DQS1p | K17 |
| DQS1n | J17 |
| DQS2p | B21 |
| DQS2n | A21 |
| DQS3p | F18 |
| DQS3n | E18 |
| DM0 | L19 |
| DM1 | L15 |
| DM2 | D20 |
| DM3 | B20 |
| ODT | H20 |
| DDR3 PIN | FPGA PIN |
|---|---|
| A0 | J21 |
| A1 | J22 |
| A2 | K21 |
| A3 | H22 |
| A4 | G13 |
| A5 | G17 |
| A6 | H15 |
| A7 | G16 |
| A8 | G20 |
| A9 | M21 |
| A10 | J15 |
| A11 | G15 |
| A12 | H13 |
| A13 | K22 |
| A14 | L21 |
| BA0 | H18 |
| BA1 | J19 |
| BA2 | H19 |
| DDR3 PIN | FPGA PIN |
|---|---|
| D0 | N18 |
| D1 | L20 |
| D2 | N20 |
| D3 | K18 |
| D4 | M18 |
| D5 | K19 |
| D6 | N19 |
| D7 | L18 |
| D8 | L16 |
| D9 | L14 |
| D10 | K14 |
| D11 | M15 |
| D12 | K16 |
| D13 | M13 |
| D14 | K13 |
| D15 | L13 |
| DDR3 PIN | FPGA PIN |
|---|---|
| D16 | D22 |
| D17 | C20 |
| D18 | E21 |
| D19 | D21 |
| D20 | G21 |
| D21 | C22 |
| D22 | E22 |
| D23 | B22 |
| D24 | A20 |
| D25 | D19 |
| D26 | A19 |
| D27 | F19 |
| D28 | C18 |
| D29 | E19 |
| D30 | A18 |
| D31 | C19 |
MIG Settings
Artix-7 devices support external, high-performance memory through the use of the Memory Interface Generator (MIG) provided by Xilinx. MIG produces a custom memory interface core that may be included in your design. These parameters have been used successfully within Opal Kelly but your design needs may require deviations.
All settings are based on MIG 4.0 and Vivado 2016.2.
External differential termination is provided for the sys_clk signal. By default the MIG core enables internal termination on these signals, causing errors at compile time. To resolve this error, edit the <mig_name>_mig.v file and change the value of DIFF_TERM_SYSCLK to “FALSE“.
| PARAMETER | XEM7310 |
|---|---|
| Controller Type | DDR3 SDRAM |
| Clock Period | 2500ps (400.00MHz) |
| PHY to Controller Clock Ratio | 4:1 |
| Vccaux_io | 1.8V |
| Memory Type | Components |
| Memory Part | MT41K256M16XX-125 |
| Memory Voltage | 1.5V |
| Data Width | 32 |
| ECC | Disabled |
| Data Mask | Enabled |
| Ordering | Normal |
| Input Clock Period | 5000ps (200MHz) |
| Read Burst Type and Length | Sequential – 8 |
| Output Driver Impedance Control | RZQ/7 |
| Controller Chip Select Pin | Disable |
| RTT (nominal) – On Die Termination (ODT) | RZQ/6 |
| Memory Address Mapping | BANK | ROW | COLUMN |
| System Clock | Differential |
| Reference Clock | Use System Clock |
| System Reset Polarity | Active High |
| Debug Signals for Memory Controller | Off |
| Internal Vref | Enabled |
| IO Power Reduction | On |
| XADC Instantiation | Enabled |
| Internal Termination Impedance | 60 Ohms |
| DCI Cascade | Disabled |
| sys_clk_p/n Bank Number | 16 |
| sys_clk_p/n Pin Number | D17/C17(CC_P/N) |
| Rtt WR – Dynamic ODT | Dynamic ODT off |
| DIFF_TERM_SYSCLK | FALSE |