Expansion Connectors

Opal Kelly Pins is an interactive online reference for the expansion connectors on all Opal Kelly FPGA integration modules. It provides additional information on pin capabilities, pin characteristics, and PCB routing.

Pins can also generate constraint files (XDC) and help you map your HDL net names to FPGA pin locations automatically.

The Pins reference for the XEM7310MT may be found at the link to the right. 

 

Connector Details

Three high-density expansion connectors are available on the bottom-side of the XEM7310MT. Two expansion connectors provide user access to several power rails on the XEM7310MT, the JTAG interface on the FPGA, and 126 I/O pins on the FPGA (including several MRCC clock inputs). A 40-pin connector provides access to the Artix-7 GTP transceivers, including both REFCLK inputs.

The 80-pin connectors on the XEM7310MT are Samtec part number: QSE-040-01-H-D-A. The 40-pin connector is Samtec part number QSE-020-01-H-D-A. The table below lists the appropriate Samtec mating connectors along with the total mated height.

SAMTEC 80-PIN PART NUMBERSAMTEC 40-PIN PART NUMBERMATED HEIGHT
QTE-040-01-F-D-AQTE-020-01-F-D-A5.00mm (0.197”)
QTE-040-02-F-D-AQTE-020-02-F-D-A8.00mm (0.315”)
QTE-040-03-F-D-AQTE-020-03-F-D-A11.00mm (0.433”)
QTE-040-04-F-D-AQTE-020-04-F-D-A16.00mm (0.634”)
QTE-040-05-F-D-AQTE-020-05-F-D-A19.00mm (0.752”)

MC1

MC1 is an 80-pin high-density connector providing access to FPGA Banks 34, 13, and 16. Several pins of this connector are wired to clock inputs on the FPGA, see the table below and the Xilinx Artix-7 documentation for more details.

Pin mappings for MC1 are listed on the pins page linked above.  For each pin, the corresponding board connection is listed.  For pins connected to the FPGA, the corresponding FPGA pin number is also shown.  Finally, for pins routed to differential pair I/Os on the FPGA, the FPGA signal names and routed track lengths have been provided to help you equalize lengths on differential pairs.

Bank 34 is powered by VCCO_MC1 which is user adjustable (see Setting the Expansion Connector I/O Voltages below). Bank 13 is powered by a fixed 3.3V supply. Bank 16 is powered by a fixed 1.5V supply.

MC2

MC2 is an 80-pin high-density connector providing access to FPGA Bank 35, 13, and 16. Several pins of this connector are wired to clock inputs on the FPGA, see the table below and the Xilinx Artix-7 documentation for more details.

Pin mappings for MC2 are listed on the pins page linked above.  For each pin, the corresponding board connection is listed.  For pins connected to the FPGA, the corresponding FPGA pin number is also shown.  Finally, for pins routed to differential pair I/Os on the FPGA, the FPGA signal names and routed track lengths have been provided to help you equalize lengths on differential pairs.

Bank 35 is powered by VCCO_MC2 which is user adjustable (see Setting the Expansion Connector I/O Voltages below). Bank 13 is powered by a fixed 3.3V supply. Bank 16 is powered by a fixed 1.5V supply.

MC3

MC3 is a 40-pin high-density connector providing access to the Artix-7 GTP transceivers, including the REFCLK inputs. The connector uses a differential pair pinout (every third pin connected to ground) to minimize crosstalk between adjacent signal pairs. For more information on using the transceivers, see Xilinx UG482.

Clock Input Pins

Available clock pins are illustrated in the table below. All pins listed are multi-region clock pins.

FPGA BANKFPGA PINSMCX PINS
Bank 34
MRCC 
V4
W4
MC1:3
MC1:1
Bank 34
MRCC 
R4
T4
MC1:32
MC1:30
Bank 35
MRCC 
H4
G4
MC2:57
MC2:59
Bank 35
MRCC 
K4
J4
MC2:50
MC2:52
Bank 13
MRCC 
V13
V14
MC2:20
MC2:22

Setting the Expansion Connector I/O Voltages

The Artix-7 FPGA allows users to set I/O bank voltages in order to support several different I/O signal standards.  This functionality is supported by the XEM7310MT by allowing the user to connect independent supplies to the FPGA VCCO pins on two of the FPGA banks.

By default, ferrite beads have been installed that attach each VCCO bank to the +3.3VDD supply.  If you intend to supply power to a particular I/O bank, you MUST remove the appropriate ferrite beads.  Power can then be supplied through the expansion connectors.

The table below lists details for user-supplied I/O bank voltages

I/O BANKSUPPLY NETEXPANSION PINSFERRITE BEAD
34VCCO_MC1MC1-74, 76FB8
35VCCO_MC2MC2-77, 79FB9

For information on FPGA power supply startup sequencing, see Powering the XEM7310MT.

XADC

The Xilinx Artix-7 XADC feature is routed through two 80.6-Ω resistors to the MC1 connector. There is a 680 pF capacitor installed across the two FPGA pins for decoupling and low-pass filtering (C46). For more detail see Xilinx UG480.

FPGA FUNCTIONFPGA PINMC1 PINRESISTOR REFDES
ADC_VN_0M972R33
ADC_VP_0L1070R32

Considerations for Differential Signals

The XEM7310MT PCB layout and routing has been designed with several applications in mind, including applications requiring the use of differential (LVDS) pairs.  Please refer to the Xilinx Artix-7 datasheet for details on using differential I/O standards with the Artix-7 FPGA.

FPGA I/O Bank Voltages

In order to use differential I/O standards with the Artix-7, you must set the VCCO voltages for the appropriate banks to 2.5 V according to the Xilinx Artix-7 datasheet.

Characteristic Impedance

The characteristic impedance of all differential routes from the FPGA to the expansion connector is approximately 100 Ω differential (approximately 50 Ω single-ended).

Differential Pair Lengths

In many cases, it is desirable that the route lengths of a differential pair be matched within some specification.  Care has been taken to route differential pairs on the FPGA to adjacent pins on the expansion connectors whenever possible. We have also included the lengths of the board routes for these connections to help you equalize lengths in your final application. Due to space constraints, some pairs are better matched than others.

Reference Voltage Pins (Vref)

The Xilinx Artix-7 supports both internal and externally-applied input voltage thresholds for some input signal standards. The XEM7310MT supports these Vref applications for banks 13, 34, and 35. Please see the Xilinx Artix 7 documentation for more details.

For Bank 34, the two Vref pins are routed to expansion connector MC1 on pins 22 and 52. Note that both pins must be connected to the same voltage for proper application of input thresholds. Please see the Xilinx Artix-7 documentation for more details.

For Bank 35, the two Vref pins are routed to expansion connector MC2 on pins 21 and 57. Note that both pins must be connected to the same voltage for proper application of input thresholds. Please see the Xilinx Artix-7 documentation for more details.

For Bank 13, the single Vref pin is routed to expansion connector MC2 on pin 74. Please see the Xilinx Artix-7 documentation for more details.

I/O State at Power On

Xilinx Artix-7 FPGAs support a weak pull-up state on all I/O pins from power on until first configuration. This behavior is controlled by the PUDC_B pin. By default the XEM7310MT holds the PUDC_B pin high with a 1kΩ resistor at R26, disabling the weak pull-up on all I/O pins at power on. This behavior can be changed by inserting a 0Ω resistor at R28 and removing the 1kΩ resistor at R26, forcing the PUDC_B pin to ground.