DDR3 Memory

The Micron DDR3 SDRAM is connected exclusively to the 1.5-v I/O on Banks 15 and 16 of the FPGA. The tables below list these connections.

The following resources are available to help provide guidance for designs that involve this memory:

  • The RAMTester sample reads and writes this memory via FrontPanel pipe endpoints.
  • The XEM7310MT Pins Reference can generate a constraints file (click on Export) with complete pin mapping and I/O constraints for use in your design.

Connection Tables

DDR3 PINFPGA PIN
RESETF21
CKpJ14
CKnH14
CKEG18
RASJ16
CASH17
WEJ20
DQS0pN22
DQS0nM22
DQS1pK17
DQS1nJ17
DQS2pB21
DQS2nA21
DQS3pF18
DQS3nE18
DM0L19
DM1L15
DM2D20
DM3B20
ODTH20
DDR3 PINFPGA PIN
A0J21
A1J22
A2K21
A3H22
A4G13
A5G17
A6H15
A7G16
A8G20
A9M21
A10J15
A11G15
A12H13
A13K22
A14L21
BA0H18
BA1J19
BA2H19
DDR3 PINFPGA PIN
D0N18
D1L20
D2N20
D3K18
D4M18
D5K19
D6N19
D7L18
D8L16
D9L14
D10K14
D11M15
D12K16
D13M13
D14K13
D15L13
DDR3 PINFPGA PIN
D16D22
D17C20
D18E21
D19D21
D20G21
D21C22
D22E22
D23B22
D24A20
D25D19
D26A19
D27F19
D28C18
D29E19
D30A18
D31C19

MIG Settings

Vivado 2018.3 introduced a bug that causes errors when verifying the pin placement for the XEM7310MT memory interface. This bug can be fixed with the patch available on this Xilinx answer record: https://www.xilinx.com/support/answers/71898.html.

Artix-7 devices support external, high-performance memory through the use of the Memory Interface Generator (MIG) provided by Xilinx. MIG produces a custom memory interface core that may be included in your design. These parameters have been used successfully within Opal Kelly but your design needs may require deviations.

All settings are based on MIG 4.0 and Vivado 2016.2.

PARAMETERXEM7310
Controller TypeDDR3 SDRAM
Clock Period2500ps (400.00MHz)
PHY to Controller Clock Ratio4:1
Vccaux_io1.8V
Memory TypeComponents
Memory PartMT41K256M16XX-125
Memory Voltage1.5V
Data Width32
ECCDisabled
Data MaskEnabled
OrderingNormal
Input Clock Period5000ps (200MHz)
Read Burst Type and LengthSequential – 8
Output Driver Impedance ControlRZQ/7
Controller Chip Select PinDisable
RTT (nominal) – On Die Termination (ODT)RZQ/6
Memory Address MappingBANK | ROW | COLUMN
System ClockDifferential
Reference ClockUse System Clock
System Reset PolarityActive High
Debug Signals for Memory ControllerOff
Internal VrefEnabled
IO Power ReductionOn
XADC InstantiationEnabled
Internal Termination Impedance60 Ohms
DCI CascadeDisabled
sys_clk_p/n Bank Number13
sys_clk_p/n Pin NumberW11/W12(CC_P/N)
Rtt WR – Dynamic ODTDynamic ODT off
DIFF_TERM_SYSCLKFALSE