Hardware Design Guide

This reference is provided to help guide you through the design process of a mating peripheral to the XEM7310MT. It is not intended to be a comprehensive instruction manual. While we put forth great effort to reduce the effort required to build an FPGA-enabled platform, there are hundreds of pages of product documentation from Xilinx that should be considered. Use this guide as a roadmap and starting point for your design effort.

Useful References

Electrical Design Guide

Input Power Supply Connection

Input power to the XEM7310MT may be applied either through the DC barrel jack or through mezzanine header MC1. For information on the barrel jack dimensions and polarity, see Powering the XEM7310MT. For information on mezzanine header pin assignments, see the XEM7310MT Pins Reference.

Total Power Budget

The total operating power budget is an important system consideration. The power budget for the XEM7310MT is highly dependent on the FPGA’s operating parameters and this can only be determined in the context of an actual target design.

The onboard XEM7310MT power supply regulators provide power for all on-board systems, including the VIO rails provided to the mezzanine headers. The Power Budget table on the Powering the XEM7310MT page indicates the total current available for each supply rail. This table may be used to estimate the total amount of input power required for your design.

FPGA I/O Bank Selection and I/O Standard

Details on the available standards can be found in the following Xilinx documentation:

  • Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS181)
  • 7 Series FPGAs SelectIO Resources (UG471)

FPGA I/O Bank Selection and Voltage

Voltage supply rails VCCO_MC1 and VCCO_MC2 power the FPGA I/O banks on mezzanine connectors MC1 and MC2, respectively. By default, these rails are powered by an on-board 3.3V regulator. Power to these rails may also be user-supplied through the mezzanine connectors – this requires removal of ferrite beads on the XEM7310MT and connection of power to the appropriate pins on the connectors. More information can be found on the Expansion Connectors page. See the XEM7310MT Pins Reference for details about FPGA bank power assignments.

Mechanical Design Guide

Mezzanine Connector Placement

Refer to the XEM7310MT mating board diagram for placement locations of the mezzanine connectors (Samtec QTE series) and mounting holes. This diagram can be found on the Specifications page of the XEM7310MT documentation.

Confirm the Connector Footprint

For recommended PCB layout of the Samtec QTE connector, refer to the QTE footprint drawing on the Samtec QTE Product Page

Confirm Mounting Hole Locations

Refer to the XEM7310MT Specifications for a comprehensive mechanical drawing. Also refer to the BRK7310MT as a reference platform. The BRK7310MT design files can be found in the Downloads section of the Pins website.

Confirm Other Mechanical Placements

Refer to the XEM7310MT mechanical drawing for locations of the USB jacks and the DC power jack. This drawing is available on the Specifications page of the XEM7310MT documentation.

Thermal Dissipation Requirements

Thermal dissipation for the XEM7310MT is highly dependent on the FPGA’s operating parameters and this can only be determined in the context of an actual target design. The type of FPGA cooling solution required for your design should be determined through thermal analysis and simulation as required.

Determine the Mated Board Stacking Height

The Samtec QSE-series connectors on the XEM7310MT mate with QTE-series connectors on the carrier board. The QTE series is available in several stacking height options from 5 to 30 mm. The stack height is determined by the “lead style” of the QTE connector.

Note that increased stack height can lead to decreased high-speed channel performance. Information on 3-dB insertion loss point is available on the Samtec website.