ZYNQ7 Processing System

The hard processor system (PS) on the Zynq 7 requires configuration to understand how to interact with the peripherals on the Brain-1. At boot, this configuration is entered into registers on the CPU through the FSBL or U-Boot SPL. Any changes made to this configuration will require generating a new hardware handoff (hdf) file along with a re-build of the U-Boot SPL or FSBL.

The configuration parameters below correspond to the configuration for the reference design provided by Opal Kelly. Applications conforming to the settings outlined below will be compatible with the reference designs and official Linux image from Opal Kelly. Other designs may require some changes to the parameters listed below, resulting in incompatibilities with the Opal Kelly U-Boot and Linux configuration.

PS-PL Configuration

PARAMETERSYZYGY BRAIN-1
General
UART0 Baud Rate115200
UART1 Baud RateN/A
Enable Clock Resets->FCLK_RESET0_NEnabled
Other settingsDefault/Disabled
AXI Non Secure Enablement0
M AXI GP0 interfaceEnabled
HP Slave AXI Interface
S AXI HP0 interfaceEnabled
S AXI HP0 DATA WIDTH64
All other settingsDefault/Disabled

Peripheral I/O Pins

MIO PIN (RANGE)ASSIGNMENT
0-11GPIO MIO
12-13I2C1
14-15UART0
16-27Enet0
28-39USB0
40-45SD0
46SD0 Card Detect
47USB PHY Reset
48-50GPIO MIO
51Ethernet PHY Reset
52-53Ethernet 0 MDIO
EMIOI2C0

MIO Configuration

This majority of this section is configured correctly according to the settings entered in the Peripheral I/O Pins section.

Bank 0 on the Brain-1 runs at 3.3V (LVCMOS 3.3V), while Bank 1 runs at 1.8V (LVCMOS 1.8V).

The following changes should be made:

I/O PERIPHERALS
SD 0
CDMIO 46
GPIO
ENET ResetShare reset pin
ENET0 ResetMIO 51
USB ResetShare reset pin
USB0 ResetMIO 47
I2C ResetShare reset pin

Clock Configuration

The PS receives a 50 MHz input clock. The reference design configures the CPU Clock Ratio to 6:2:1.

COMPONENTCLOCK SOURCEREQUESTED FREQUENCY (MHZ)
Processor/Memory Clocks
CPUARM PLL666.666
DDRDDR PLL533.333
IO Peripheral Clocks
ENET0IO PLL1000 Mbps
SDIOIO PLL100
PL Fabric Clocks
FCLK_CLK0IO PLL125
FCLK_CLK1IO PLL40
FCLK_CLK2IO PLL24
FCLK_CLK3IO PLL200

DDR Configuration

(see the DDR3 Memory page)

Interrupts

All Fabric Interrupts are disabled by default in the reference design.